Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751730AbdFIMSj (ORCPT ); Fri, 9 Jun 2017 08:18:39 -0400 Received: from mail-ot0-f179.google.com ([74.125.82.179]:36380 "EHLO mail-ot0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751556AbdFIMSh (ORCPT ); Fri, 9 Jun 2017 08:18:37 -0400 MIME-Version: 1.0 In-Reply-To: <1497005895.28352.88.camel@nxp.com> References: <7055ce6095c0b7f026ac6f0dc37e43fc5c0b1793.1496939031.git.leonard.crestez@nxp.com> <1497005895.28352.88.camel@nxp.com> From: Fabio Estevam Date: Fri, 9 Jun 2017 09:18:35 -0300 Message-ID: Subject: Re: [PATCH 2/2] ARM: dts: imx6ul: Add imx6ul-tempmon To: Leonard Crestez Cc: Shawn Guo , Bai Ping , "linux-pm@vger.kernel.org" , linux-kernel , Eduardo Valentin , Sascha Hauer , Fabio Estevam , Zhang Rui , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 865 Lines: 16 On Fri, Jun 9, 2017 at 7:58 AM, Leonard Crestez wrote: > Yes, as far as I can tell the tempmon block uses the 480 Mhz PLL3 clock > directly. This is similar to other imx6 SOCs. This PLL is used for > stuff like USB but not only that. My understanding is the _USB_OTG > suffix is descriptive, similar to PLL4_AUDIO and PLL6_ENET. Other non- > usb components use PLL3 (like UART) but through other gates/dividers. Yes, PLL3 can be a parent for the UART clock, but UART has its own clock gate. > Setting this to IMX6UL_CLK_DUMMY will cause temperature reads to fail. > Even if PLL3 usually ends up being constantly enabled because of uarts > this is not true at imx_thermal_probe time (or uarts can be disabled). Ok, thanks for confirming. It was not obvious from reading the reference manual that the PLL3 clock is the gate for tempmon.