Date: Fri, 9 Jun 2017 14:47:48 +0100
From: Will Deacon <will.deacon@arm.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>, linux-arch@vger.kernel.org,
        linux-kernel@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>,
        olof@lixom.net, albert@sifive.com, patches@groups.riscv.org,
        Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH 10/17] irqchip: New RISC-V PLIC Driver
Message-ID: <20170609134748.GL13955@arm.com>
References: <20170523004107.536-1-palmer@dabbelt.com>
 <20170606230007.19101-1-palmer@dabbelt.com>
 <20170606230007.19101-11-palmer@dabbelt.com>
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On Wed, Jun 07, 2017 at 11:52:10AM +0100, Marc Zyngier wrote:
> On 07/06/17 00:00, Palmer Dabbelt wrote:
> > +static void plic_disable(struct plic_data *data, int i, int hwirq)
> > +{
> > +	struct plic_enable_context *enable = plic_enable_context(data, i);
> > +
> > +	atomic_and(~(1 << (hwirq % 32)), &enable->mask[hwirq / 32]);
> 
> This is still a device access, right? What does it mean to use the
> atomic primitives on that? What are you racing against? I thought the
> various context were private to an execution context...
> 
> Adding Will and PeterZ to the CC list because they will probably have
> their own views on this...

atomic_* accesses to MMIO is almost certainly a bad idea. Is this atomic
because you want to allow the function to run concurrently, or is it atomic
because you want some guarantees from the endpoint's view?

Will