Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751984AbdFIN4V (ORCPT ); Fri, 9 Jun 2017 09:56:21 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:1174 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751867AbdFIN4R (ORCPT ); Fri, 9 Jun 2017 09:56:17 -0400 Message-ID: <1497016569.29586.36.camel@mtksdaap41> Subject: Re: [PATCH v2 2/2] arm64: dts: Add Mediatek SoC MT2712 and evaluation board dts and Makefile From: YT Shen To: Matthias Brugger CC: Rob Herring , Mark Rutland , Thomas Gleixner , Jason Cooper , Marc Zyngier , Greg Kroah-Hartman , Catalin Marinas , Will Deacon , Mars Cheng , , , , , , Date: Fri, 9 Jun 2017 21:56:09 +0800 In-Reply-To: <92e438b3-4e9c-421b-5398-5aad2541524c@gmail.com> References: <1496230773-22633-1-git-send-email-yt.shen@mediatek.com> <1496230773-22633-3-git-send-email-yt.shen@mediatek.com> <92e438b3-4e9c-421b-5398-5aad2541524c@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 7480 Lines: 272 On Wed, 2017-05-31 at 14:42 +0200, Matthias Brugger wrote: > > On 31/05/17 13:39, YT Shen wrote: > > This adds basic chip support for Mediatek 2712 > > > > Signed-off-by: YT Shen > > --- > > arch/arm64/boot/dts/mediatek/Makefile | 1 + > > arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 39 +++++++ > > arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 166 ++++++++++++++++++++++++++++ > > 3 files changed, 206 insertions(+) > > create mode 100644 arch/arm64/boot/dts/mediatek/mt2712-evb.dts > > create mode 100644 arch/arm64/boot/dts/mediatek/mt2712e.dtsi > > > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > > index 9fbfd32..fcc0604 100644 > > --- a/arch/arm64/boot/dts/mediatek/Makefile > > +++ b/arch/arm64/boot/dts/mediatek/Makefile > > @@ -1,3 +1,4 @@ > > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb > > diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts > > new file mode 100644 > > index 0000000..e526c0f > > --- /dev/null > > +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts > > @@ -0,0 +1,39 @@ > > +/* > > + * Copyright (c) 2017 MediaTek Inc. > > + * Author: YT Shen > > + * > > + * SPDX-License-Identifier: (GPL-2.0 OR MIT) > > + */ > > + > > +/dts-v1/; > > +#include "mt2712e.dtsi" > > + > > +/ { > > + model = "MediaTek MT2712 evaluation board"; > > + compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; > > + > > + aliases { > > + serial0 = &uart0; > > + serial1 = &uart1; > > + serial2 = &uart2; > > + serial3 = &uart3; > > + serial4 = &uart4; > > + serial5 = &uart5; > > + }; > > Just declare serial0 here, as you don't use the others. Ok, will remove the others. Sorry for the late reply. > > + > > + memory@40000000 { > > + device_type = "memory"; > > + reg = <0 0x40000000 0 0x80000000>; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:921600n8"; > > + linux,initrd-start = <0x45000000>; > > + linux,initrd-end = <0x4a000000>; > > initrd-start and end should be dynamically set by the bootloader and not > via a chosen node. Is your bootloader not able to do that? OK, will remove initrd start and end later. Yes, current bootloader I used is new development and it does not send any parameters now > > > + }; > > +}; > > + > > +&uart0 { > > + status = "okay"; > > +}; > > + > > diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > > new file mode 100644 > > index 0000000..6df0da9 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi > > @@ -0,0 +1,166 @@ > > +/* > > + * Copyright (c) 2017 MediaTek Inc. > > + * Author: YT Shen > > + * > > + * SPDX-License-Identifier: (GPL-2.0 OR MIT) > > + */ > > + > > +#include > > +#include > > + > > +/ { > > + compatible = "mediatek,mt2712"; > > + interrupt-parent = <&sysirq>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&cpu0>; > > + }; > > + core1 { > > + cpu = <&cpu1>; > > + }; > > + }; > > + > > + cluster1 { > > + core0 { > > + cpu = <&cpu2>; > > + }; > > + }; > > + }; > > + > > + cpu0: cpu@0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a35"; > > do you mean cortex-a53? No, the cpu is cortex-a35. Although I cannot find other cortex-a35 description in mainline kernel. Thanks for the review. yt.shen > > > + reg = <0x000>; > > + }; > > + > > + cpu1: cpu@1 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a35"; > > same here. > > Regards, > Matthias > > > + reg = <0x001>; > > + enable-method = "psci"; > > + }; > > + > > + cpu2: cpu@200 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a72"; > > + reg = <0x200>; > > + enable-method = "psci"; > > + }; > > + }; > > + > > + psci { > > + compatible = "arm,psci-0.2"; > > + method = "smc"; > > + }; > > + > > + uart_clk: dummy26m { > > + compatible = "fixed-clock"; > > + clock-frequency = <26000000>; > > + #clock-cells = <0>; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupt-parent = <&gic>; > > + interrupts = > + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, > > + > + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, > > + > + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, > > + > + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; > > + }; > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + compatible = "simple-bus"; > > + ranges; > > + > > + uart5: serial@1000f000 { > > + compatible = "mediatek,mt2712-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x1000f000 0 0x400>; > > + interrupts = ; > > + clocks = <&uart_clk>; > > + status = "disabled"; > > + }; > > + > > + sysirq: interrupt-controller@10220a80 { > > + compatible = "mediatek,mt2712-sysirq", > > + "mediatek,mt6577-sysirq"; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + interrupt-parent = <&gic>; > > + reg = <0 0x10220a80 0 0x40>; > > + }; > > + > > + gic: interrupt-controller@10510000 { > > + compatible = "arm,gic-400"; > > + #interrupt-cells = <3>; > > + interrupt-parent = <&gic>; > > + interrupt-controller; > > + reg = <0 0x10510000 0 0x1000>, > > + <0 0x10520000 0 0x1000>, > > + <0 0x10540000 0 0x2000>, > > + <0 0x10560000 0 0x2000>; > > + interrupts = > + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; > > + }; > > + > > + uart0: serial@11002000 { > > + compatible = "mediatek,mt2712-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x11002000 0 0x400>; > > + interrupts = ; > > + clocks = <&uart_clk>; > > + status = "disabled"; > > + }; > > + > > + uart1: serial@11003000 { > > + compatible = "mediatek,mt2712-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x11003000 0 0x400>; > > + interrupts = ; > > + clocks = <&uart_clk>; > > + status = "disabled"; > > + }; > > + > > + uart2: serial@11004000 { > > + compatible = "mediatek,mt2712-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x11004000 0 0x400>; > > + interrupts = ; > > + clocks = <&uart_clk>; > > + status = "disabled"; > > + }; > > + > > + uart3: serial@11005000 { > > + compatible = "mediatek,mt2712-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x11005000 0 0x400>; > > + interrupts = ; > > + clocks = <&uart_clk>; > > + status = "disabled"; > > + }; > > + > > + uart4: serial@11019000 { > > + compatible = "mediatek,mt2712-uart", > > + "mediatek,mt6577-uart"; > > + reg = <0 0x11019000 0 0x400>; > > + interrupts = ; > > + clocks = <&uart_clk>; > > + status = "disabled"; > > + }; > > + }; > > +}; > > + > >