Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751799AbdFIWjw (ORCPT ); Fri, 9 Jun 2017 18:39:52 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:35678 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751633AbdFIWju (ORCPT ); Fri, 9 Jun 2017 18:39:50 -0400 From: Joshua Clayton To: Alan Tull , Moritz Fischer , Anatolij Gustschin , Bastian Stender , Shawn Guo , Joshua Clayton Cc: Rob Herring , Mark Rutland , Sascha Hauer , Fabio Estevam , Russell King , linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v13 1/6] fpga: Add flag to indicate SPI bitstream is bit-reversed Date: Fri, 9 Jun 2017 15:39:34 -0700 Message-Id: <03e591707dc72f4c2b5e63a1272060956294ea51.1497047816.git.stillcompiling@gmail.com> X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1578 Lines: 42 From: Anatolij Gustschin Add a flag that is passed to the write_init() callback, indicating that the SPI bitstream starts with LSB first. SPI controllers usually send data with MSB first. If an FPGA expects bitstream data as LSB first, the data must be reversed either by the SPI controller or by the driver. Alternatively the bitstream could be prepared as bit-reversed to avoid the bit-swapping while sending. This flag indicates such bit-reversed SPI bitstream. The low-level driver will deal with the flag and perform bit-reversing if needed. Signed-off-by: Anatolij Gustschin Signed-off-by: Joshua Clayton --- Changes since v12: - Change "depends on SPI || COMPILE_TEST" to "depends on SPI" in patch 3 include/linux/fpga/fpga-mgr.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index b4ac24c4411d..01c348ca38b7 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -67,10 +67,12 @@ enum fpga_mgr_states { * FPGA Manager flags * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting + * FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first */ #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) +#define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) /** * struct fpga_image_info - information specific to a FPGA image -- 2.11.0