Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751996AbdFKWh1 (ORCPT ); Sun, 11 Jun 2017 18:37:27 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:59529 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751878AbdFKWh0 (ORCPT ); Sun, 11 Jun 2017 18:37:26 -0400 From: Chris Packham To: =?iso-8859-1?Q?Jan_L=FCbbe?= CC: "bp@alien8.de" , "linux-arm-kernel@lists.infradead.org" , "linux-edac@vger.kernel.org" , Mauro Carvalho Chehab , "linux-kernel@vger.kernel.org" Subject: Re: [RFC PATCH 1/4] EDAC: mvebu: Add driver for Marvell Armada SoCs Thread-Topic: [RFC PATCH 1/4] EDAC: mvebu: Add driver for Marvell Armada SoCs Thread-Index: AQHS4A1SaAGhpKz8JUKL1XuS2Mm6yg== Date: Sun, 11 Jun 2017 22:37:18 +0000 Message-ID: <1ddc23d9f25c4952a1ca04d20cbb598c@svr-chch-ex1.atlnz.lc> References: <20170608041124.4624-1-chris.packham@alliedtelesis.co.nz> <20170608041124.4624-2-chris.packham@alliedtelesis.co.nz> <1497014062.3536.52.camel@pengutronix.de> Accept-Language: en-NZ, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [2001:df5:b000:22:78c1:f648:bf50:be35] Content-Type: text/plain; charset="iso-8859-1" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v5BMbWsv026106 Content-Length: 984 Lines: 23 On 10/06/17 01:19, Jan L?bbe wrote: >> + >> + if (edac_op_state == EDAC_OPSTATE_INT) { >> + /* acquire interrupt that reports errors */ >> + pdata->irq = platform_get_irq(pdev, 0); >> + res = devm_request_irq(&pdev->dev, >> + pdata->irq, >> + mvebu_mc_isr, >> + 0, >> + "[EDAC] MC err", >> + mci); > Which IRQ do you use? The current DT doesn't configure interrupts. Also > it seems that the events are passed through additional layers of > mask/status registers which are not yet represented in the Armada-XP IRQ > hierarchy. So my driver currently uses polling. Yes I'd been forcing polling too. To get this working properly I think we'd need to add another irqchip driver for the SoC Err interrupts. Which is kind of where I'd got stuck, the datasheet is a little confusing in that area. I think I'd figured out that the root interrupt comes through INT 4 which could be cascaded to the as yet unwritten SoC Err irqchip.