Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752078AbdFLOZT (ORCPT ); Mon, 12 Jun 2017 10:25:19 -0400 Received: from mx08-00252a01.pphosted.com ([91.207.212.211]:58274 "EHLO mx08-00252a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752076AbdFLOZR (ORCPT ); Mon, 12 Jun 2017 10:25:17 -0400 From: Phil Elwell Subject: [PATCH v2 0/4] Add bcm2835aux interrupt controller To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Florian Fainelli , Stefan Wahren , Eric Anholt , Russell King , Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-clk@vger.kernel.org Message-ID: <4ceb6c92-f752-180e-6a6e-a94dcd120737@raspberrypi.org> Date: Mon, 12 Jun 2017 15:25:02 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-06-12_10:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_notspam policy=outbound_spam score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=15 spamscore=0 clxscore=1015 lowpriorityscore=15 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706120249 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1966 Lines: 40 Devices in the BCM2835 AUX block share a common interrupt line, with a register indicating which devices have active IRQs. Expose this as a nested interrupt controller to avoid IRQ sharing problems (easily observed if UART1 and SPI1/2 are enabled simultaneously). This patch set is complicated by the fact that the DT node for the AUX clock controller includes the AUXIRQ register needed by this driver. Patch 1 lays the groundwork by allowing this overlap and preparing for a future DT change that removes it. Changes in v2: * Add DT bindings and header file for bcm2835-aux-intc. * Split the interrupt-controller functionality into a dedicated irqchip driver with a dedicated DT node. * Remove mask tracking from the intc driver, so that all interrupts (including spurious ones) are submitted to the IRQ framework. * Replace hard-coded masks with BIT macro in the intc driver. * Prepare the AUX clock driver for a time when its DT node may only be a single word register, but until then ioremap its region without reserving it to permit sharing. Phil Elwell (4): clk: bcm2835: More flexible IO register remapping dt: bindings: Add bindings for bcm2835-aux-intc irqchip: Add BCM2835 AUX interrupt controller ARM: dts: bcm283x: Add and use bcm2835-aux-intc .../interrupt-controller/brcm,bcm2835-aux-intc.txt | 28 ++++ arch/arm/boot/dts/bcm283x.dtsi | 27 +++- drivers/clk/bcm/clk-bcm2835-aux.c | 20 ++- drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-bcm2835-aux.c | 155 +++++++++++++++++++++ .../interrupt-controller/bcm2835-aux-intc.h | 20 +++ 6 files changed, 243 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-aux-intc.txt create mode 100644 drivers/irqchip/irq-bcm2835-aux.c create mode 100644 include/dt-bindings/interrupt-controller/bcm2835-aux-intc.h -- 1.9.1