Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932106AbdFLPh3 (ORCPT ); Mon, 12 Jun 2017 11:37:29 -0400 Received: from mail-co1nam03on0086.outbound.protection.outlook.com ([104.47.40.86]:58720 "EHLO NAM03-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754101AbdFLPhY (ORCPT ); Mon, 12 Jun 2017 11:37:24 -0400 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com; From: Dong Aisheng To: CC: , , , , , , , , , , , Dong Aisheng Subject: [PATCH V3 0/7] tty: serial: lpuart: add imx7ulp support Date: Mon, 12 Jun 2017 23:37:21 +0800 Message-ID: <1497281848-12995-1-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 X-EOPAttributedMessage: 0 X-Matching-Connectors: 131417554413504323;(91ab9b29-cfa4-454e-5278-08d120cd25b8);() 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1;BL2PR03MB161;7:L+q0dMuK9Cm27odiRbYko7Z14sCUK8Jzj6VVTppwUsdxcKi3FnWZG+tDGjH5bbZnqNqgJ1RnZxWS4xyWeaboOghgn22W22gugwKw5VFRJrwjSGFh3Bi0cqh/SDCgtE6JpDSFW6e2nXwDTwRMgT8d1yk2sUMTgfTQO/8gbzi54dTYrEk3aD16Us6uUAv2dUmcl6Vs2CcA+SeHn7k4L9hODX/vDUzcB9RLQANh9xevr8SirTwZlGWGbIi0vQq1BLejQioCLWukvazHBLEEroRGTcbWy/UC8DeazzKY4A51XKUOgge99Lfkt5hFGCZ8bq96LML1jtOLMA2cUHe8cr4O8A== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2017 15:37:21.0228 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;Ip=[192.88.168.50];Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2PR03MB161 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2189 Lines: 54 This patch series mainly intends to add imx7ulp support which is also using FSL lpuart. The lpuart in imx7ulp is basically the same as ls1021a. It's also 32 bit width register, but unlike ls1021a, it's little endian. Besides that, imx7ulp lpuart has a minor different register layout from ls1021a that it has four extra registers (verid, param, global, pincfg) located at the beginning of register map, which are currently not used by the driver and less to be used later. Furthermore, this patch serial also add a new more accurate baud rate calculation method as MX7ULP can't divide a suitable baud rate with the default setting. Currently the new baud rate calculation is only enabled on MX7ULP. However, i guess the Layerscape may also be able to use it as there seems to be no difference in baud rate setting register after checking the Layerscape Reference Manual. As i don't have Layerscape boards, i can't test it, so i only enable it for MX7ULP by default to avoid a potential break. I copied LayerScape guys in this series and hope they can help test later. If it works on Layerscape as well, then they can switch to the new setting too and totally remove the old stuff. ChangeLog: v2->v3: * Remove global lpuart_is_be. Instead use struct uart_port's iotype member. lpuart32_read/write API prototype is also updated to use the iotype to distingush the endians. And most importantly, this way also works with earlycon. v1->v2: * Patch 2/4/5 chagned, other no changes. See individuals for details. Dong Aisheng (7): tty: serial: lpuart: introduce lpuart_soc_data to represent SoC property tty: serial: lpuart: refactor lpuart32_{read|write} prototype tty: serial: lpuart: add little endian 32 bit register support dt-bindings: serial: fsl-lpuart: add i.MX7ULP support tty: serial: lpuart: add imx7ulp support tty: serial: lpuart: add earlycon support for imx7ulp tty: serial: lpuart: add a more accurate baud rate calculation method .../devicetree/bindings/serial/fsl-lpuart.txt | 2 + drivers/tty/serial/fsl_lpuart.c | 286 ++++++++++++++------- 2 files changed, 201 insertions(+), 87 deletions(-) -- 2.7.4