Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754564AbdFLQr0 (ORCPT ); Mon, 12 Jun 2017 12:47:26 -0400 Received: from mail.linuxfoundation.org ([140.211.169.12]:41360 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753732AbdFLPfZ (ORCPT ); Mon, 12 Jun 2017 11:35:25 -0400 From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Marc Zyngier , Christoffer Dall Subject: [PATCH 4.9 041/119] KVM: arm/arm64: vgic-v3: Do not use Active+Pending state for a HW interrupt Date: Mon, 12 Jun 2017 17:25:03 +0200 Message-Id: <20170612152559.301783194@linuxfoundation.org> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170612152556.601664278@linuxfoundation.org> References: <20170612152556.601664278@linuxfoundation.org> User-Agent: quilt/0.65 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1376 Lines: 42 4.9-stable review patch. If anyone has any objections, please let me know. ------------------ From: Marc Zyngier commit 3d6e77ad1489650afa20da92bb589c8778baa8da upstream. When an interrupt is injected with the HW bit set (indicating that deactivation should be propagated to the physical distributor), special care must be taken so that we never mark the corresponding LR with the Active+Pending state (as the pending state is kept in the physycal distributor). Fixes: 59529f69f504 ("KVM: arm/arm64: vgic-new: Add GICv3 world switch backend") Signed-off-by: Marc Zyngier Reviewed-by: Christoffer Dall Signed-off-by: Christoffer Dall Signed-off-by: Greg Kroah-Hartman --- virt/kvm/arm/vgic/vgic-v3.c | 7 +++++++ 1 file changed, 7 insertions(+) --- a/virt/kvm/arm/vgic/vgic-v3.c +++ b/virt/kvm/arm/vgic/vgic-v3.c @@ -151,6 +151,13 @@ void vgic_v3_populate_lr(struct kvm_vcpu if (irq->hw) { val |= ICH_LR_HW; val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; + /* + * Never set pending+active on a HW interrupt, as the + * pending state is kept at the physical distributor + * level. + */ + if (irq->active && irq->pending) + val &= ~ICH_LR_PENDING_BIT; } else { if (irq->config == VGIC_CONFIG_LEVEL) val |= ICH_LR_EOI;