Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752873AbdFLSYb (ORCPT ); Mon, 12 Jun 2017 14:24:31 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:35074 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752850AbdFLSY2 (ORCPT ); Mon, 12 Jun 2017 14:24:28 -0400 From: Steve Longerbeam X-Google-Original-From: Steve Longerbeam To: Shawn Guo , Sascha Hauer , Fabio Estevam , Rob Herring , Mark Rutland , Russell King Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Steve Longerbeam Subject: [PATCH 09/11] ARM: dts: imx6-sabreauto: add reset-gpios property for max7310_b Date: Mon, 12 Jun 2017 11:24:02 -0700 Message-Id: <1497291844-14632-10-git-send-email-steve_longerbeam@mentor.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497291844-14632-1-git-send-email-steve_longerbeam@mentor.com> References: <1497291844-14632-1-git-send-email-steve_longerbeam@mentor.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1211 Lines: 40 The reset pin to the port expander chip (MAX7310) is controlled by a gpio, so define a reset-gpios property to control it. There are three MAX7310's on the SabreAuto CPU card (max7310_[abc]), but all use the same pin for their reset. Since all can't acquire the same pin, assign it to max7310_b, that chip is needed by more functions (usb and adv7180). Signed-off-by: Steve Longerbeam --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index c8e35c4..21dea5f 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -136,6 +136,9 @@ reg = <0x32>; gpio-controller; #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max7310>; + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; max7310_c: gpio@34 { @@ -441,6 +444,12 @@ >; }; + pinctrl_max7310: max7310grp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + pinctrl_pwm3: pwm1grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -- 2.7.4