Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752514AbdFMFzZ convert rfc822-to-8bit (ORCPT ); Tue, 13 Jun 2017 01:55:25 -0400 Received: from mail.ginzinger.com ([31.193.165.229]:24515 "EHLO mail.ginzinger.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752455AbdFMFzX (ORCPT ); Tue, 13 Jun 2017 01:55:23 -0400 From: =?iso-8859-1?Q?Sch=F6fegger_Stefan?= To: Richard Zhu CC: Bjorn Helgaas , "linux-pci@vger.kernel.org" , Arnd Bergmann , open list , Kishon Vijay Abraham I , Jingoo Han , Bjorn Helgaas , "moderated list:PCI DRIVER FOR IMX6" , Lucas Stach Subject: Re: [PATCH v2 1/1] PCI: imx6: Add pcie compliance test option Thread-Topic: [PATCH v2 1/1] PCI: imx6: Add pcie compliance test option Thread-Index: AQHS34JNOUvPfo4UA0OvE2IoSGw1A6IhzH4AgAAkkACAAEGfAA== Date: Tue, 13 Jun 2017 05:55:09 +0000 Message-ID: <1782110.RW4F1b4ZIY@en-pc05> References: <1472121518-9340-1-git-send-email-stefan.schoefegger@ginzinger.com> <20170612234924.GE4379@bhelgaas-glaptop.roam.corp.google.com> In-Reply-To: Accept-Language: de-DE, en-US Content-Language: de-DE X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.2.1.54] Content-Type: text/plain; charset="iso-8859-1" Content-ID: <76D352A606110046B100285A83863410@ginzinger.com> Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4515 Lines: 108 On Tuesday, June 13, 2017 2:00:16 AM CEST Richard Zhu wrote: > > -----Original Message----- > > From: Bjorn Helgaas [mailto:helgaas@kernel.org] > > Sent: Tuesday, June 13, 2017 7:49 AM > > To: Stefan Schoefegger > > Cc: linux-pci@vger.kernel.org; Richard Zhu ; Arnd > > Bergmann ; open list ; > > Kishon Vijay Abraham I ; Jingoo Han > > ; Bjorn Helgaas ; > > moderated list:PCI DRIVER FOR IMX6 ; > > Lucas Stach > > Subject: Re: [PATCH v2 1/1] PCI: imx6: Add pcie compliance test option > > > > On Wed, Jun 07, 2017 at 01:36:11PM +0200, Stefan Schoefegger wrote: > > > Link speed must not be limited to gen1 during link test for compliance > > > tests > > > > > > Signed-off-by: Stefan Schoefegger > > > --- > > > > > > Changes since v1: > > > - pci-imx6.c moved to dwc directory > > > > > > drivers/pci/dwc/Kconfig | 10 ++++++++++ > > > drivers/pci/dwc/pci-imx6.c | 21 ++++++++++++--------- > > > 2 files changed, 22 insertions(+), 9 deletions(-) > > > > > > diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index > > > b7e15526d676..b6e9ced5a45d 100644 > > > --- a/drivers/pci/dwc/Kconfig > > > +++ b/drivers/pci/dwc/Kconfig > > > @@ -77,6 +77,16 @@ config PCI_IMX6 > > > > > > select PCIEPORTBUS > > > select PCIE_DW_HOST > > > > > > +config PCI_IMX6_COMPLIANCE_TEST > > > + bool "Enable pcie compliance tests on imx6" > > > + depends on PCI_IMX6 > > > + default n > > > + help > > > + Enables support for pcie compliance test on FSL iMX SoCs. > > > + The link speed wouldn't be limited to gen1 when enabled. > > > + Enable only during compliance tests, otherwise > > > + link detection will fail on some peripherals. > > > > I'm puzzled about why we would want to merge this patch. It looks like > > we're trying to game the system to make the device pass compliance testing > > when it isn't really compliant. Is this config option useful to users, or > > is it only useful during internal development of iMX SoCs? > > [Zhu hongxing] Agree with Bjorn. These modifications shouldn't be merged. > They are used for the boards used to pass the PCIe RC certification, when > one Standalone external OSC is used as PCIe reference clock source in the > boards design. Yes, passing gen2 compliance test is only possible with external clk. But this is a errata of imx6 pci phy of PCIe clk jitter. Why should we not be able to do gen2 tests? I think it is useful to do other gen2 tests (signal integrity) during board design. > > > config PCIE_SPEAR13XX > > > > > > bool "STMicroelectronics SPEAr PCIe controller" > > > depends on PCI > > > > > > diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c > > > index 19a289b8cc94..b0fbe52e25b0 100644 > > > --- a/drivers/pci/dwc/pci-imx6.c > > > +++ b/drivers/pci/dwc/pci-imx6.c > > > @@ -533,15 +533,18 @@ static int imx6_pcie_establish_link(struct > > > > imx6_pcie *imx6_pcie) > > > > > u32 tmp; > > > int ret; > > > > > > - /* > > > - * Force Gen1 operation when starting the link. In case the link is > > > - * started in Gen2 mode, there is a possibility the devices on the > > > - * bus will not be detected at all. This happens with PCIe switches. > > > - */ > > > - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); > > > - tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; > > > - tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; > > > - dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); > > > + if (!IS_ENABLED(CONFIG_PCI_IMX6_COMPLIANCE_TEST)) { > > > + /* > > > + * Force Gen1 operation when starting the link. In case the > > > + * link is started in Gen2 mode, there is a possibility the > > > + * devices on the bus will not be detected at all. This > > > + * happens with PCIe switches. > > > + */ > > > + tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); > > > + tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; > > > + tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; > > > + dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); > > > + } > > > > > > /* Start LTSSM. */ > > > if (imx6_pcie->variant == IMX7D) > > > > > > -- > > > 2.11.0 > > > > > > > > > _______________________________________________ > > > linux-arm-kernel mailing list > > > linux-arm-kernel@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel