Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754202AbdFNGCf (ORCPT ); Wed, 14 Jun 2017 02:02:35 -0400 Received: from mail-wr0-f177.google.com ([209.85.128.177]:33208 "EHLO mail-wr0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750745AbdFNGCd (ORCPT ); Wed, 14 Jun 2017 02:02:33 -0400 MIME-Version: 1.0 In-Reply-To: <20170613.173318.167061176274123943.davem@davemloft.net> References: <149737430797.28477.9215445312169809396.sendpatchset@little-apple> <20170613.173318.167061176274123943.davem@davemloft.net> From: Magnus Damm Date: Wed, 14 Jun 2017 15:02:30 +0900 Message-ID: Subject: Re: [PATCH] via-rhine: add support for changing MTU To: David Miller Cc: netdev , linux-kernel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1817 Lines: 46 On Wed, Jun 14, 2017 at 6:33 AM, David Miller wrote: > From: Magnus Damm > Date: Wed, 14 Jun 2017 02:18:27 +0900 > >> From: Magnus Damm >> >> Allow adjusting the MTU for via-rhine devices in case of no TX alignment >> buffer is used. >> >> Lightly tested on ALIX2D13 hardware by making use of VXLAN with MTU set >> to 1500 on top of via-rhine devices with 1550 MTU. Without this patch >> the VXLAN MTU is limited to less than 1500. >> >> Signed-off-by: Magnus Damm > > Why is the TX alignment buffer such an obstacle? Not such a big obstacle - I simply took the easy way out for this first step. Adding support for MTU configuration when TX alignment is required requires a bit more effort, and it also makes the driver implementation slightly more complex. The particular silicon version of via-rhine devices on my ALIX2D13 boards do not require the TX alignment workaround, but I should be able to add some local test code for development purpose. As for the TX alignment workaround implementation, when needed the driver allocates rp->tx_bufs to PKT_BUF_SIZE * TX_RING_SIZE. To support a larger MTU setting without increasing default memory usage this TX side can be adjusted to manage buffers in a more dynamic way, perhaps similar to the RX side with rp->rx_buf_sz. > It would be so much nicer if this could be supported for all chip > variants instead of some certain subset which users have no idea > of figuring out. It's a really bad user experience to set them > up for failure like this. Sure, I agree! Will update the code with the TX alignment workaround and resend after some much needed testing. It will most likely take some time, so please don't block anything on this. Cheers, / magnus