Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752450AbdFNPfZ (ORCPT ); Wed, 14 Jun 2017 11:35:25 -0400 Received: from mail-ot0-f196.google.com ([74.125.82.196]:35804 "EHLO mail-ot0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752348AbdFNPfX (ORCPT ); Wed, 14 Jun 2017 11:35:23 -0400 Date: Wed, 14 Jun 2017 10:35:21 -0500 From: Rob Herring To: Mark Yao Cc: David Airlie , Mark Rutland , Heiko Stuebner , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/3] drm/rockchip: dw_hdmi: introduce the VPLL clock setting Message-ID: <20170614153521.fr75vwkbx65i56jf@rob-hp-laptop> References: <1496992228-10582-1-git-send-email-mark.yao@rock-chips.com> <1496992242-10681-1-git-send-email-mark.yao@rock-chips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1496992242-10681-1-git-send-email-mark.yao@rock-chips.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 769 Lines: 20 On Fri, Jun 09, 2017 at 03:10:41PM +0800, Mark Yao wrote: > For RK3399 HDMI, there is an external clock need for HDMI PHY, > and it should keep the same clock rate with VOP DCLK. > > VPLL have supported the clock for HDMI PHY, but there is no > clock divider bewteen VPLL and HDMI PHY. So we need to set the > VPLL rate manually in HDMI driver. > > Signed-off-by: Yakir Yang > Signed-off-by: Mark Yao > --- > Changes in v3: none > Changes in v2: describe vpll on Documentation. > > .../bindings/display/rockchip/dw_hdmi-rockchip.txt | 2 +- Acked-by: Rob Herring > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 25 +++++++++++++++++++++- > 2 files changed, 25 insertions(+), 2 deletions(-)