Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752059AbdFOKVm (ORCPT ); Thu, 15 Jun 2017 06:21:42 -0400 Received: from mga09.intel.com ([134.134.136.24]:13187 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750777AbdFOKVl (ORCPT ); Thu, 15 Jun 2017 06:21:41 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,343,1493708400"; d="scan'208";a="1141522750" Date: Thu, 15 Jun 2017 13:21:35 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Xiaoguang Chen Cc: alex.williamson@redhat.com, kraxel@redhat.com, chris@chris-wilson.co.uk, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, zhenyuw@linux.intel.com, zhiyuan.lv@intel.com, intel-gvt-dev@lists.freedesktop.org, zhi.a.wang@intel.com, kevin.tian@intel.com Subject: Re: [Intel-gfx] [PATCH v9 3/7] drm: Extend the drm format Message-ID: <20170615102135.GT12629@intel.com> References: <1497513611-2814-1-git-send-email-xiaoguang.chen@intel.com> <1497513611-2814-4-git-send-email-xiaoguang.chen@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1497513611-2814-4-git-send-email-xiaoguang.chen@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1421 Lines: 42 On Thu, Jun 15, 2017 at 04:00:07PM +0800, Xiaoguang Chen wrote: > Add new drm format which will be used by GVT-g. > > Signed-off-by: Xiaoguang Chen > --- > include/uapi/drm/drm_fourcc.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h > index 55e3010..2681862 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -113,6 +113,10 @@ extern "C" { > > #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ > > +/* 64 bpp RGB */ > +#define DRM_FORMAT_XRGB161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ > +#define DRM_FORMAT_XBGR161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ Are these supposed to be the half float formats? If so the docs are lacking. Also this sort of stuff must be sent to dri-devel for everyone to see. That said, I don't really like having them in any gvt code until they're handled by the driver proper. > + > /* > * 2 plane RGB + A > * index 0 = RGB plane, same format as the corresponding non _A8 format has > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel OTC