Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752667AbdFOUm6 (ORCPT ); Thu, 15 Jun 2017 16:42:58 -0400 Received: from anholt.net ([50.246.234.109]:57180 "EHLO anholt.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752577AbdFOUlh (ORCPT ); Thu, 15 Jun 2017 16:41:37 -0400 From: Eric Anholt To: dri-devel@lists.freedesktop.org, Archit Taneja , Andrzej Hajda , Laurent Pinchart , Thierry Reding , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Eric Anholt Subject: [PATCH 2/7] drm/vc4: Fix DSI T_INIT timing. Date: Thu, 15 Jun 2017 13:41:25 -0700 Message-Id: <20170615204130.19255-3-eric@anholt.net> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170615204130.19255-1-eric@anholt.net> References: <20170615204130.19255-1-eric@anholt.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1420 Lines: 34 The DPHY spec requires a much larger T_INIT than I was specifying before. In the absence of clear specs from the slave of what their timing is, just use the value that the firmware was using. Signed-off-by: Eric Anholt --- drivers/gpu/drm/vc4/vc4_dsi.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c index 5e8b81eaa168..15f6d5005ab9 100644 --- a/drivers/gpu/drm/vc4/vc4_dsi.c +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -1035,7 +1035,17 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder) DSI_HS_DLT4_TRAIL) | VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT)); - DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000, 5000), + /* T_INIT is how long STOP is driven after power-up to + * indicate to the slave (also coming out of power-up) that + * master init is complete, and should be greater than the + * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The + * D-PHY spec gives a minimum 100us for T_INIT,MASTER and + * T_INIT,SLAVE, while allowing protocols on top of it to give + * greater minimums. The vc4 firmware uses an extremely + * conservative 5ms, and we maintain that here. + */ + DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, + 5 * 1000 * 1000, 0), DSI_HS_DLT5_INIT)); DSI_PORT_WRITE(HS_DLT6, -- 2.11.0