Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752445AbdFOW2K (ORCPT ); Thu, 15 Jun 2017 18:28:10 -0400 Received: from mail-it0-f43.google.com ([209.85.214.43]:36652 "EHLO mail-it0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751893AbdFOW2H (ORCPT ); Thu, 15 Jun 2017 18:28:07 -0400 MIME-Version: 1.0 In-Reply-To: References: <1497534989-29231-1-git-send-email-eranian@google.com> <20170615151018.GA4789@tassilo.jf.intel.com> <20170615172320.GB4789@tassilo.jf.intel.com> <20170615200205.GC4789@tassilo.jf.intel.com> From: Stephane Eranian Date: Thu, 15 Jun 2017 15:28:06 -0700 Message-ID: Subject: Re: [PATCH 0/5] perf: add support for capturing skid IP To: Andi Kleen Cc: LKML , Arnaldo Carvalho de Melo , Peter Zijlstra , "mingo@elte.hu" , "Liang, Kan" , Jiri Olsa Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2475 Lines: 52 On Thu, Jun 15, 2017 at 1:20 PM, Stephane Eranian wrote: > On Thu, Jun 15, 2017 at 1:02 PM, Andi Kleen wrote: >> On Thu, Jun 15, 2017 at 12:35:39PM -0700, Stephane Eranian wrote: >>> On Thu, Jun 15, 2017 at 10:23 AM, Andi Kleen wrote: >>> > On Thu, Jun 15, 2017 at 09:44:07AM -0700, Stephane Eranian wrote: >>> >> On Thu, Jun 15, 2017 at 8:10 AM, Andi Kleen wrote: >>> >> > On Thu, Jun 15, 2017 at 06:56:24AM -0700, Stephane Eranian wrote: >>> >> >> This patchs adds a new sample record type called >>> >> >> PERF_SAMPLE_SKID_IP. The goal is to record >>> >> >> the unmodified interrupted instruction pointer (IP) as seen by >>> >> >> the kernel and reflected in the machine state. >>> >> > >>> >> > Patches look reasonable for me. >>> >> > >>> >> > If you only cared about branches it would be more natural to model >>> >> > it like a 1 entry LBR. That would make a lot more tooling work >>> >> > automatically. >>> >> > >>> >> You'd still have to modify tooling to present correct column headers. >>> > >>> > Why? It's from/to? >>> > >>> Ah, yes you are right, but it is not clear to me how you would specify >>> this cleanly with the interface. >>> Especially in the case where this could be used for non-branch instructions. >> >> Generally the skid ip is only interesting for instructions that have some kind of >> control flow change, or an exception/interrupt. >> > True, right now I found use for the control flow changes, but any PEBS enabled > event + precise=2 could potentially be useful. >> So if it's interesting the headers would be correct. >> >> Actually it's even correct for non control flow change, because the IP >> moves from "FROM" to "TO" ... >> > Sure. > But I am not too fond of tying this to a branch abstraction. You'd > have to express > this with the perf_events interface.To trigger LBR-style hardware, you'd have > to define a new PERF_SAMPLE_BRANCH_SKID_IP of some sort and then you > tie this to a branch kind of sampling feature: > > $ perf record -j skid_ip -e BR_INST_RETIRED.CONDITIONAL:pp > > Is what I think you are thinking about. Looking at this approach, the user interface is straightforward, implementation in the x86 code is a bit more hairy because of the way the branch_stack is captured, via the cpuc->lbr_entries. If you assume that SKID_IP cannot be used with any other branch stack mode, then it is easy. It becomes messy if you don't.