Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754368AbdFPOuo (ORCPT ); Fri, 16 Jun 2017 10:50:44 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:7876 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754330AbdFPOum (ORCPT ); Fri, 16 Jun 2017 10:50:42 -0400 Subject: Re: [PATCH v5 15/20] arm64: dts: hisi: add kirin pcie node To: Guodong Xu , , , , , , , , , , , References: <20170615030417.14059-16-guodong.xu@linaro.org> <20170616141322.30466-1-guodong.xu@linaro.org> CC: , , , , , , Xiaowei Song From: Wei Xu Message-ID: <5943EE79.1050505@hisilicon.com> Date: Fri, 16 Jun 2017 15:43:05 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <20170616141322.30466-1-guodong.xu@linaro.org> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.181.154] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0203.5943EE90.010C,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 12f1207158da2dbdbb0d18671fd363dc Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2200 Lines: 73 Hi Guodong, On 2017/6/16 15:13, Guodong Xu wrote: > From: Xiaowei Song > > Add PCIe node for hi3660 > > Cc: Guodong Xu > Signed-off-by: Xiaowei Song > Acked-by: Arnd Bergmann > > Changes in v5: > * fix interrupt-map, to conform to gic's #address-cells = <0> > * remove redundant status = "ok" > --- Thanks! Applied v5 and dropped the v4 in the hisilicon arm64 dt tree. BR, Wei > arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 36 +++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > index e138973..8183d71 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > @@ -754,5 +754,41 @@ > cs-gpios = <&gpio18 5 0>; > status = "disabled"; > }; > + > + pcie@f4000000 { > + compatible = "hisilicon,kirin960-pcie"; > + reg = <0x0 0xf4000000 0x0 0x1000>, > + <0x0 0xff3fe000 0x0 0x1000>, > + <0x0 0xf3f20000 0x0 0x40000>, > + <0x0 0xf5000000 0x0 0x2000>; > + reg-names = "dbi", "apb", "phy", "config"; > + bus-range = <0x0 0x1>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x02000000 0x0 0x00000000 > + 0x0 0xf6000000 > + 0x0 0x02000000>; > + num-lanes = <1>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0xf800 0 0 7>; > + interrupt-map = <0x0 0 0 1 > + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, > + <0x0 0 0 2 > + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, > + <0x0 0 0 3 > + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, > + <0x0 0 0 4 > + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, > + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, > + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; > + clock-names = "pcie_phy_ref", "pcie_aux", > + "pcie_apb_phy", "pcie_apb_sys", > + "pcie_aclk"; > + reset-gpios = <&gpio11 1 0 >; > + }; > }; > }; >