Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752023AbdFSRcq (ORCPT ); Mon, 19 Jun 2017 13:32:46 -0400 Received: from mail-qt0-f172.google.com ([209.85.216.172]:35734 "EHLO mail-qt0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751965AbdFSRcn (ORCPT ); Mon, 19 Jun 2017 13:32:43 -0400 Subject: Re: [PATCH v3 0/4] Generalize fncpy availability To: Mark Rutland , Florian Fainelli Cc: linux-arm-kernel@lists.infradead.org, "open list:GENERIC INCLUDE/ASM HEADER FILES" , Arnd Bergmann , Dave Gerlach , Tony Lindgren , Catalin Marinas , Will Deacon , Russell King , open list , bcm-kernel-feedback-list@broadcom.com, Greg Kroah-Hartman , Alexandre Belloni , linux-omap@vger.kernel.org, Shawn Guo , Keerthy J References: <20170617000744.22158-1-f.fainelli@gmail.com> <20170619122444.GJ10246@leverpostej> From: Florian Fainelli Message-ID: Date: Mon, 19 Jun 2017 10:32:38 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <20170619122444.GJ10246@leverpostej> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1711 Lines: 47 On 06/19/2017 05:24 AM, Mark Rutland wrote: > On Fri, Jun 16, 2017 at 05:07:40PM -0700, Florian Fainelli wrote: >> Hi all, > > Hi Florian, > >> This patch series makes ARM's fncpy() implementation more generic (dropping the >> Thumb-specifics) and available in an asm-generic header file. >> >> Tested on a Broadcom ARM64 STB platform with code that is written to SRAM. >> >> Changes in v3 (thanks Doug!): >> - correct include guard names in asm-generic/fncpy.h to __ASM_FNCPY_H >> - utilize Kbuild to provide the fncpy.h header on ARM64 >> >> Changes in v2: >> - leave the ARM implementation where it is >> - make the generic truly generic (no) >> >> This is helpful in making SoC-specific power management code become true drivers >> that can be shared between different architectures. > > Could you elaborate on what this is needed for? Several uses cases come to mind: - it could be used as a trampoline code prior to entering S2 for systems that do not support PSCI 1.0 - any code that has a specific need to relocate a performance, security sensitive code into SRAM and use it as another pool of memory. > > My understanding was that on 32-bit, this was to handle idle / suspend > cases, whereas for arm64 that should be handled by PSCI. For systems that support PSCI 1.0, I agree, but it may not be possible to update those systems easily, still use case 2 is completely valid. > > what exactly do you intend to use this for? At the moment we use it to enter S2 on ARM64 systems (ARCH_BRCMSTB) which are PSCI 0.2 only. And yes, we do have a plan to evaluate upgrading to PSCI 1.0, but in general, any SoC which as an addressable SRAM could use it for whatever purpose it sees fit. -- Florian