Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751131AbdFTBpR (ORCPT ); Mon, 19 Jun 2017 21:45:17 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:39916 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751019AbdFTBpO (ORCPT ); Mon, 19 Jun 2017 21:45:14 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 37C3C60A3B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Mon, 19 Jun 2017 18:45:12 -0700 From: Stephen Boyd To: Dong Aisheng Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com, shawnguo@kernel.org, Anson.Huang@nxp.com, ping.bai@nxp.com Subject: Re: [PATCH 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE clk support Message-ID: <20170620014512.GL4493@codeaurora.org> References: <1494856763-6543-1-git-send-email-aisheng.dong@nxp.com> <1494856763-6543-2-git-send-email-aisheng.dong@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1494856763-6543-2-git-send-email-aisheng.dong@nxp.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1128 Lines: 30 On 05/15, Dong Aisheng wrote: > --- > drivers/clk/clk-divider.c | 2 ++ > include/linux/clk-provider.h | 4 ++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c > index 96386ff..f78ba7a 100644 > --- a/drivers/clk/clk-divider.c > +++ b/drivers/clk/clk-divider.c > @@ -125,6 +125,8 @@ unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, > > div = _get_div(table, val, flags, divider->width); > if (!div) { > + if (flags & CLK_DIVIDER_ZERO_GATE) > + return 0; > WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO), Why not use the CLK_DIVIDER_ALLOW_ZERO flag? A clk being off doesn't mean the rate is 0. The divider is just disabled, so we would consider the rate as whatever the parent is, which is what this code does before this patch. Similarly, we don't do anything about gate clocks and return a rate of 0 when they're disabled. > "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", > clk_hw_get_name(hw)); -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project