Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752651AbdFTCBY (ORCPT ); Mon, 19 Jun 2017 22:01:24 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:51834 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750992AbdFTCBV (ORCPT ); Mon, 19 Jun 2017 22:01:21 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3539660D0C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Mon, 19 Jun 2017 19:01:19 -0700 From: Stephen Boyd To: Dong Aisheng Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com, shawnguo@kernel.org, Anson.Huang@nxp.com, ping.bai@nxp.com Subject: Re: [PATCH 9/9] clk: imx: add imx7ulp clk driver Message-ID: <20170620020119.GQ4493@codeaurora.org> References: <1494856763-6543-1-git-send-email-aisheng.dong@nxp.com> <1494856763-6543-10-git-send-email-aisheng.dong@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1494856763-6543-10-git-send-email-aisheng.dong@nxp.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1387 Lines: 36 On 05/15, Dong Aisheng wrote: > + > + clks[IMX7ULP_CLK_VIU] = imx_clk_gate("viu", "nic1_clk", base + 0xA0, 30); > + clks[IMX7ULP_CLK_PCTLC] = imx_clk_gate("pctlc", "nic1_bus_clk", base + 0xB8, 30); > + clks[IMX7ULP_CLK_PCTLD] = imx_clk_gate("pctld", "nic1_bus_clk", base + 0xBC, 30); > + clks[IMX7ULP_CLK_PCTLE] = imx_clk_gate("pctle", "nic1_bus_clk", base + 0xc0, 30); > + clks[IMX7ULP_CLK_PCTLF] = imx_clk_gate("pctlf", "nic1_bus_clk", base + 0xc4, 30); > + > + clks[IMX7ULP_CLK_GPU3D] = imx_clk_composite("gpu3d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140); > + clks[IMX7ULP_CLK_GPU2D] = imx_clk_composite("gpu2d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144); > + > + imx_check_clocks(clks, ARRAY_SIZE(clks)); > + > + clk_data.clks = clks; > + clk_data.clk_num = ARRAY_SIZE(clks); > + of_clk_add_provider(scg_node, of_clk_src_onecell_get, &clk_data); Please use of_clk_add_hw_provider() instead, and the associated clk_hw registration APIs. > + > + pr_info("i.MX7ULP clock tree init done.\n"); pr_debug? > +} > + > +CLK_OF_DECLARE(imx7ulp, "fsl,imx7ulp-clock", imx7ulp_clocks_init); > Any reason why it can't be a platform driver? If not, please add some comment explaining why. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project