Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752620AbdFTJC0 (ORCPT ); Tue, 20 Jun 2017 05:02:26 -0400 Received: from mga04.intel.com ([192.55.52.120]:34141 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750846AbdFTJCX (ORCPT ); Tue, 20 Jun 2017 05:02:23 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,364,1493708400"; d="scan'208";a="99688418" From: "Zhang, Tina" To: =?utf-8?B?VmlsbGUgU3lyasOkbMOk?= , "Chen, Xiaoguang" CC: "intel-gfx@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , "kraxel@redhat.com" , "intel-gvt-dev@lists.freedesktop.org" , "Lv, Zhiyuan" , "Wang, Zhi A" , "Wang, Zhenyu Z" Subject: RE: [Intel-gfx] [PATCH v9 3/7] drm: Extend the drm format Thread-Topic: [Intel-gfx] [PATCH v9 3/7] drm: Extend the drm format Thread-Index: AQHS5a2XDFmtxA8eBUelntwZbcqO9qIlMN2AgAhKTwA= Date: Tue, 20 Jun 2017 09:01:59 +0000 Message-ID: <237F54289DF84E4997F34151298ABEBC7C56EC31@SHSMSX101.ccr.corp.intel.com> References: <1497513611-2814-1-git-send-email-xiaoguang.chen@intel.com> <1497513611-2814-4-git-send-email-xiaoguang.chen@intel.com> <20170615102135.GT12629@intel.com> In-Reply-To: <20170615102135.GT12629@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v5K92UMB025255 Content-Length: 2277 Lines: 64 > -----Original Message----- > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of > Ville Syrjälä > Sent: Thursday, June 15, 2017 6:22 PM > To: Chen, Xiaoguang > Cc: intel-gfx@lists.freedesktop.org; linux-kernel@vger.kernel.org; > kraxel@redhat.com; intel-gvt-dev@lists.freedesktop.org; Lv, Zhiyuan > > Subject: Re: [Intel-gfx] [PATCH v9 3/7] drm: Extend the drm format > > On Thu, Jun 15, 2017 at 04:00:07PM +0800, Xiaoguang Chen wrote: > > Add new drm format which will be used by GVT-g. > > > > Signed-off-by: Xiaoguang Chen > > --- > > include/uapi/drm/drm_fourcc.h | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/include/uapi/drm/drm_fourcc.h > > b/include/uapi/drm/drm_fourcc.h index 55e3010..2681862 100644 > > --- a/include/uapi/drm/drm_fourcc.h > > +++ b/include/uapi/drm/drm_fourcc.h > > @@ -113,6 +113,10 @@ extern "C" { > > > > #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] > A:Y:Cb:Cr 8:8:8:8 little endian */ > > > > +/* 64 bpp RGB */ > > +#define DRM_FORMAT_XRGB161616 fourcc_code('X', 'R', '4', '8') /* > > +[63:0] x:R:G:B 16:16:16:16 little endian */ #define > > +DRM_FORMAT_XBGR161616 fourcc_code('X', 'B', '4', '8') /* [63:0] > > +x:B:G:R 16:16:16:16 little endian */ > > Are these supposed to be the half float formats? If so the docs are lacking. Also > this sort of stuff must be sent to dri-devel for everyone to see. > > That said, I don't really like having them in any gvt code until they're handled by > the driver proper. This is needed by some Apps running on Windows VM. These can be separated to another patch set where more can be included, e.g. docs. Thanks. > > > + > > /* > > * 2 plane RGB + A > > * index 0 = RGB plane, same format as the corresponding non _A8 > > format has > > -- > > 2.7.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx