Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753035AbdFTJTp (ORCPT ); Tue, 20 Jun 2017 05:19:45 -0400 Received: from mx07-00252a01.pphosted.com ([62.209.51.214]:27678 "EHLO mx07-00252a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752757AbdFTJTK (ORCPT ); Tue, 20 Jun 2017 05:19:10 -0400 Subject: Re: [PATCH v3 3/4] irqchip: Add BCM2835 AUX interrupt controller To: Florian Fainelli , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland , Stefan Wahren , Eric Anholt , Russell King , Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-clk@vger.kernel.org References: <4ceb6c92-f752-180e-6a6e-a94dcd120737@raspberrypi.org> <1497457750-35585-1-git-send-email-phil@raspberrypi.org> <1497457750-35585-4-git-send-email-phil@raspberrypi.org> From: Phil Elwell Message-ID: <9e8dcada-2000-e899-2a2c-ab54ae19e3db@raspberrypi.org> Date: Tue, 20 Jun 2017 10:19:06 +0100 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.2.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-06-20_05:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_notspam policy=outbound_spam score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706200168 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1210 Lines: 33 On 19/06/2017 22:13, Florian Fainelli wrote: > On 06/14/2017 09:29 AM, Phil Elwell wrote: >> Devices in the BCM2835 AUX block share a common interrupt line, with a >> register indicating which devices have active IRQs. Expose this as a >> nested interrupt controller to avoid IRQ sharing problems (easily >> observed if UART1 and SPI1/2 are enabled simultaneously). >> >> Signed-off-by: Phil Elwell >> --- > >> +/* >> + * The irq_mask and irq_unmask function pointers are used without >> + * validity checks, so they must not be NULL. Create a dummy function >> + * with the expected type for use as a no-op. >> + */ >> +static void bcm2835_aux_irq_dummy(struct irq_data *data) >> +{ >> +} >> + >> +static struct irq_chip bcm2835_aux_irq_chip = { >> + .name = "bcm2835-aux_irq", >> + .irq_mask = bcm2835_aux_irq_dummy, >> + .irq_unmask = bcm2835_aux_irq_dummy, >> +}; > > So how are the interrupt enabled/disabled if this interrupt controller > just returns their pending state? Interrupts must be enabled, disabled and acknowledged on the blocks in the AUX domain - UART1, SPI1 and SPI2. There is no additional masking - AUXIRQ is essentially an interrupt sharing accelerator. Phil