Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752855AbdFTJU5 (ORCPT ); Tue, 20 Jun 2017 05:20:57 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:58932 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752745AbdFTJLb (ORCPT ); Tue, 20 Jun 2017 05:11:31 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6B11E60A3B Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=varada@codeaurora.org From: Varadarajan Narayanan To: broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Cc: Varadarajan Narayanan Subject: [PATCH v3 04/15] spi: qup: Add completion timeout Date: Tue, 20 Jun 2017 14:40:46 +0530 Message-Id: <1497949857-1852-5-git-send-email-varada@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1497949857-1852-1-git-send-email-varada@codeaurora.org> References: <1497949857-1852-1-git-send-email-varada@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2525 Lines: 74 Add i/o completion timeout for DMA and PIO modes. Signed-off-by: Andy Gross Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 59e799f..d3ccf53 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -330,7 +330,8 @@ static void spi_qup_dma_terminate(struct spi_master *master, dmaengine_terminate_all(master->dma_rx); } -static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer) +static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer, + unsigned long timeout) { struct spi_qup *qup = spi_master_get_devdata(master); int ret; @@ -353,10 +354,17 @@ static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer) dma_async_issue_pending(master->dma_tx); } + if (xfer->rx_buf && !wait_for_completion_timeout(&qup->rxc, timeout)) + return -ETIMEDOUT; + + if (xfer->tx_buf && !wait_for_completion_timeout(&qup->txc, timeout)) + return -ETIMEDOUT; + return 0; } -static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer) +static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer, + unsigned long timeout) { struct spi_qup *qup = spi_master_get_devdata(master); int ret; @@ -375,6 +383,9 @@ static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer) spi_qup_fifo_write(qup, xfer); + if (!wait_for_completion_timeout(&qup->done, timeout)) + return -ETIMEDOUT; + return 0; } @@ -618,7 +629,6 @@ static int spi_qup_transfer_one(struct spi_master *master, timeout = DIV_ROUND_UP(xfer->len * 8, timeout); timeout = 100 * msecs_to_jiffies(timeout); - spin_lock_irqsave(&controller->lock, flags); controller->xfer = xfer; controller->error = 0; @@ -629,10 +639,10 @@ static int spi_qup_transfer_one(struct spi_master *master, if (spi_qup_is_dma_xfer(controller->mode)) { reinit_completion(&controller->rxc); reinit_completion(&controller->txc); - ret = spi_qup_do_dma(master, xfer); + ret = spi_qup_do_dma(master, xfer, timeout); } else { reinit_completion(&controller->done); - ret = spi_qup_do_pio(master, xfer); + ret = spi_qup_do_pio(master, xfer, timeout); } if (ret) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation