Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752843AbdFVHWK (ORCPT ); Thu, 22 Jun 2017 03:22:10 -0400 Received: from regular1.263xmail.com ([211.150.99.131]:59342 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752613AbdFVHVQ (ORCPT ); Thu, 22 Jun 2017 03:21:16 -0400 X-263anti-spam: X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ABS-CHECKED: 4 X-RL-SENDER: frank.wang@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: frank.wang@rock-chips.com X-UNIQUE-TAG: <6951f28548d2be08b79d756f63ac6a3e> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Frank Wang To: heiko@sntech.de, robh+dt@kernel.org, ulf.hansson@linaro.org, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, charles.chen@rock-chips.com, kevan.lan@rock-chips.com, huangtao@rock-chips.com, finley.xiao@rock-chips.com, david.wu@rock-chips.com, shawn.lin@rock-chips.com, chenjh@rock-chips.com, wmc@rock-chips.com, Frank Wang Subject: [PATCH v2 1/7] ARM: dts: rockchip: add cpu enable method for rk3228 SoC Date: Thu, 22 Jun 2017 15:20:49 +0800 Message-Id: <1498116055-20977-2-git-send-email-frank.wang@rock-chips.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1498116055-20977-1-git-send-email-frank.wang@rock-chips.com> References: <1498116055-20977-1-git-send-email-frank.wang@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1327 Lines: 58 This patch sets PSCI as the default cpu enable-method for RK3228 SoC. Signed-off-by: Frank Wang --- arch/arm/boot/dts/rk322x.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 31e04e9..34d175e 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -70,6 +70,7 @@ #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; + enable-method = "psci"; }; cpu1: cpu@f01 { @@ -78,6 +79,7 @@ reg = <0xf01>; resets = <&cru SRST_CORE1>; operating-points-v2 = <&cpu0_opp_table>; + enable-method = "psci"; }; cpu2: cpu@f02 { @@ -86,6 +88,7 @@ reg = <0xf02>; resets = <&cru SRST_CORE2>; operating-points-v2 = <&cpu0_opp_table>; + enable-method = "psci"; }; cpu3: cpu@f03 { @@ -94,6 +97,7 @@ reg = <0xf03>; resets = <&cru SRST_CORE3>; operating-points-v2 = <&cpu0_opp_table>; + enable-method = "psci"; }; }; @@ -151,6 +155,11 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured; -- 2.0.0