Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753094AbdFVI1N (ORCPT ); Thu, 22 Jun 2017 04:27:13 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:7926 "EHLO szxga03-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752890AbdFVI1L (ORCPT ); Thu, 22 Jun 2017 04:27:11 -0400 Subject: Re: [PATCH 2/5] dt-bindings: phy-hisi-inno-usb2: add support for hisi-inno-usb2 phy To: , , References: <1498035645-22804-1-git-send-email-xuejiancheng@hisilicon.com> <1498035645-22804-3-git-send-email-xuejiancheng@hisilicon.com> CC: , , , , , , From: Jiancheng Xue Message-ID: <4134ff2a-4be7-4e32-5d2c-2dc0eb19ea86@hisilicon.com> Date: Thu, 22 Jun 2017 16:23:05 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <1498035645-22804-3-git-send-email-xuejiancheng@hisilicon.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.245.43] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.594B7E8B.0034,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: cf59729bcc5d28627b6c5c152db78467 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2282 Lines: 62 Hi, On 2017/6/21 17:00, Jiancheng Xue wrote: > Add support for hisi-inno-usb2 phy. > > Signed-off-by: Jiancheng Xue > --- > .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 36 ++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt > > diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt > new file mode 100644 > index 0000000..21f8208 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt > @@ -0,0 +1,36 @@ > +HiSilicon INNO USB2 PHY > +----------------------- > +Required properties: > +- compatible: Should be one of the following strings: > + "hisilicon,inno-usb2-phy", > + "hisilicon,hi3798cv200-usb2-phy", > +- #phy-cells: Must be 0 > +- hisilicon,peripheral-syscon: Phandle of syscon used to control phy. Here a property should be added to supply offsets of phy specific registers in the above peripheral syscon. I will modify this in the next version. --- Regards, Jiancheng > +- clocks: Phandle and clock specifier pair for reference clock utmi_refclk. > +- resets: List of phandle and reset specifier pairs for each reset signal in > +reset-names. > +- reset-names: Should be "por_rst" and "test_rst". The test_rst only > +exists in some of SOCs, so it is optional. > + > +Phy node can include up to four subnodes. Each subnode represents one port. > +The required properties of port node are as follows: > +- clocks: Phandle and clock specifier pair for utmi_clock. > +- resets: List of phandle and reset specifier pairs for port reset and utmi reset. > +- reset-names: List of reset signal names. Should be "port_rst" and "utmi_rst" > + > +Refer to phy/phy-bindings.txt for the generic PHY binding properties > + > +Example: > +usb_phy: phy { > + compatible = "hisilicon,inno_usb2_phy"; > + #phy-cells = <0>; > + hisilicon,peripheral-syscon = <&peri_ctrl>; > + clocks = <&crg USB2_REF_CLK>; > + resets = <&crg 0xb4 2>; > + reset-names = "por_rst"; > + port0 { > + clocks = <&crg USB2_UTMI0_CLK>; > + resets = <&crg 0xb4 5>, <&crg 0xb4 1>; > + reset-names = "port_rst", "utmi_rst"; > + }; > + }; >