Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753111AbdFVI7u (ORCPT ); Thu, 22 Jun 2017 04:59:50 -0400 Received: from regular1.263xmail.com ([211.150.99.140]:41365 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752783AbdFVI7s (ORCPT ); Thu, 22 Jun 2017 04:59:48 -0400 X-263anti-spam: X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ABS-CHECKED: 4 X-RL-SENDER: zhengyang@rock-chips.com X-FST-TO: kieran.bingham+renesas@ideasonboard.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zhengyang@rock-chips.com X-UNIQUE-TAG: <04c3e1859d6b32bed792c8dc1fd30807> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Reply-To: yang.zheng@rock-chips.com Subject: Re: [PATCH] drm: bridge: synopsys/dw-hdmi: Provide default configuration function for HDMI 2.0 PHY To: Mark yao , Jose Abreu , Laurent Pinchart Cc: Laurent Pinchart , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Carlos Palminha , Kieran Bingham References: <6071fd12-2cda-cd1f-2607-9a498f588040@synopsys.com> <3690108.zYIGBGnVBz@avalon> <1941ce39-1a8e-5e16-bdc2-71d988ee00d6@synopsys.com> <594B7EE3.9050202@rock-chips.com> From: Zheng Yang Organization: =?UTF-8?B?56aP5bee55Ge6Iqv5b6u55S15a2Q5pyJ6ZmQ5YWs5Y+4?= Message-ID: <70ca4634-1b1e-33c5-e50b-615e68095b37@rock-chips.com> Date: Thu, 22 Jun 2017 16:59:23 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <594B7EE3.9050202@rock-chips.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4488 Lines: 122 Hi, Jose： The value of RK3399 reg HDMI_CONFIG2_ID is 0xf3. Using hdmi_phy_configure_dwc_hdmi_3d_tx() for hdmi 2.0 phy, we test all HDMI video mode(including 594MHz) and it woks good. And our customer has pass the HDMI CTS. If you send a patch with a general config function for HDMI 2.0 phys, we can test it on our platform. 福州瑞芯微电子股份有限公司 郑阳 Email: zhengyang@rock-chips.com 在 2017年06月22日 16:25, Mark yao 写道: > Hi Jose > > Sorry miss your email and Sorry for the late reply > > I can sure that your patch works on our rk3399 platform. > > my internal kernel already has similar patch, using > hdmi_phy_configure_dwc_hdmi_3d_tx() for hdmi 2.0 phy, > good works with many video modes (4k, 1080p, 720p etc.), I'm not > familiar with hdmi, but hdmi display actually works for us. > > And, I had tried the 4.12-rc1 kernel with your patch, display works good. > > So: > Tested-by: Mark Yao > > On 2017年06月13日 22:11, Jose Abreu wrote: >> Hi Laurent, >> >> >> Sorry for the late reply! >> >> >> On 10-06-2017 09:50, Laurent Pinchart wrote: >>> Hi Jose, >>> >>> On Friday 09 Jun 2017 13:53:12 Jose Abreu wrote: >>>> On 09-06-2017 12:04, Jose Abreu wrote: >>>>> Currently HDMI 2.0 PHYs do not have a default configuration function. >>>>> >>>>> As these PHYs have the same register layout as the 3D PHYs we can >>>>> safely use the default configuration function. >>>> I may have been a little to fast arriving at this conclusion. I >>>> mean most of the registers match but in the configuration >>>> function there are registers that do not match. Did you actually >>>> test this configuration function with an HDMI 2.0 phy? And did >>>> you test with different video modes? From my experience the phy >>>> may be wrongly configured and sometimes work anyway. >>>> >>>> Do please retest with as many video modes as you can and give me >>>> your phy ID (read from controller config reg HDMI_CONFIG2_ID). >>> The Renesas R-Car Gen3 HDMI PHY reports an DWC HDMI 2.0 TX PHY ID, >>> but has a >>> configuration function (rcar_hdmi_phy_configure() in >>> drivers/gpu/drm/rcar- >>> du/rcar_dw_hdmi.c) that doesn't match >>> hdmi_phy_configure_dwc_hdmi_3d_tx(). >>> From the information I have been given the layout of the configuration >>> registers haven't been changed by Renesas. I know we've briefly >>> discussed this >>> in the past, but I'd appreciate if you could have a second look and >>> tell me >>> what you think. >> Yup, yours seems correct. Though at the time you submitted I >> found it odd that only 3 registers needed to be written whilst >> for HDMI 2.0 phys I have here 6 registers, but you said it is >> working so I though your phy was different ... >> >> Even so, one thing I would like to know is what was the max >> resolution you tested? I see you have clock values up to 297MHz, >> so 4k@30Hz? If I send a patch with a general config function for >> HDMI 2.0 phys can you test it on your platform? >> >> Best regards, >> Jose Miguel Abreu >> >>>>> If, for some reason, >>>>> >>>>> the PHY is custom this change will not make any impact because >>>>> in configuration function we prefer the pdata provided configuration >>>>> function over the internal one. >>>>> >>>>> This patch is based on today's drm-misc-next branch. >>>>> >>>>> Signed-off-by: Jose Abreu >>>>> Cc: Kieran Bingham >>>>> Cc: Laurent Pinchart >>>>> Cc: Archit Taneja >>>>> Cc: Andrzej Hajda >>>>> Cc: Mark Yao >>>>> Cc: Carlos Palminha >>>>> --- >>>>> >>>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 + >>>>> 1 file changed, 1 insertion(+) >>>>> >>>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>>>> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index ead1124..10c8d8c >>>>> 100644 >>>>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c >>>>> @@ -2170,6 +2170,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void >>>>> *dev_id) >>>>> .name = "DWC HDMI 2.0 TX PHY", >>>>> .gen = 2, >>>>> .has_svsret = true, >>>>> + .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, >>>>> }, { >>>>> .type = DW_HDMI_PHY_VENDOR_PHY, >>>>> .name = "Vendor PHY", >> >> >> > >