Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753036AbdFVLNL (ORCPT ); Thu, 22 Jun 2017 07:13:11 -0400 Received: from terminus.zytor.com ([65.50.211.136]:40027 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752630AbdFVLNJ (ORCPT ); Thu, 22 Jun 2017 07:13:09 -0400 Date: Thu, 22 Jun 2017 04:09:28 -0700 From: tip-bot for Kan Liang Message-ID: Cc: jolsa@redhat.com, alexander.shishkin@linux.intel.com, tglx@linutronix.de, stable@vger.kernel.org, linux-kernel@vger.kernel.org, torvalds@linux-foundation.org, Kan.liang@intel.com, peterz@infradead.org, mingo@kernel.org, acme@redhat.com, hpa@zytor.com Reply-To: tglx@linutronix.de, alexander.shishkin@linux.intel.com, jolsa@redhat.com, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, peterz@infradead.org, mingo@kernel.org, Kan.liang@intel.com, hpa@zytor.com, acme@redhat.com In-Reply-To: <20170619142609.11058-1-kan.liang@intel.com> References: <20170619142609.11058-1-kan.liang@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/urgent] perf/x86/intel: Add 1G DTLB load/store miss support for SKL Git-Commit-ID: fb3a5055cd7098f8d1dd0cd38d7172211113255f X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2034 Lines: 51 Commit-ID: fb3a5055cd7098f8d1dd0cd38d7172211113255f Gitweb: http://git.kernel.org/tip/fb3a5055cd7098f8d1dd0cd38d7172211113255f Author: Kan Liang AuthorDate: Mon, 19 Jun 2017 07:26:09 -0700 Committer: Ingo Molnar CommitDate: Thu, 22 Jun 2017 11:07:08 +0200 perf/x86/intel: Add 1G DTLB load/store miss support for SKL Current DTLB load/store miss events (0x608/0x649) only counts 4K,2M and 4M page size. Need to extend the events to support any page size (4K/2M/4M/1G). The complete DTLB load/store miss events are: DTLB_LOAD_MISSES.WALK_COMPLETED 0xe08 DTLB_STORE_MISSES.WALK_COMPLETED 0xe49 Signed-off-by: Kan Liang Cc: Cc: Alexander Shishkin Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: eranian@google.com Link: http://lkml.kernel.org/r/20170619142609.11058-1-kan.liang@intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/intel/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a6d91d4..110ce82 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -431,11 +431,11 @@ static __initconst const u64 skl_hw_cache_event_ids [ C(DTLB) ] = { [ C(OP_READ) ] = { [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */ - [ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ + [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */ }, [ C(OP_WRITE) ] = { [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */ - [ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */ + [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */ }, [ C(OP_PREFETCH) ] = { [ C(RESULT_ACCESS) ] = 0x0,