Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753283AbdFVLPd (ORCPT ); Thu, 22 Jun 2017 07:15:33 -0400 Received: from mail-ot0-f195.google.com ([74.125.82.195]:32822 "EHLO mail-ot0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753261AbdFVLPa (ORCPT ); Thu, 22 Jun 2017 07:15:30 -0400 MIME-Version: 1.0 In-Reply-To: References: <20170618015855.27738-1-chunyan.zhang@spreadtrum.com> <20170618015855.27738-8-chunyan.zhang@spreadtrum.com> <20170620013710.GJ4493@codeaurora.org> From: Arnd Bergmann Date: Thu, 22 Jun 2017 13:15:24 +0200 X-Google-Sender-Auth: Jchfx4eCfkE9TGsXgvgKLjZotOw Message-ID: Subject: Re: [PATCH V1 7/9] clk: sprd: add adjustable pll support To: Chunyan Zhang Cc: Stephen Boyd , Chunyan Zhang , Michael Turquette , Rob Herring , Mark Rutland , linux-clk , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Mark Brown , Xiaolong Zhang , Orson Zhai , Geng Ren , Ben Li Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1503 Lines: 38 On Thu, Jun 22, 2017 at 12:17 PM, Chunyan Zhang wrote: > On 20 June 2017 at 09:37, Stephen Boyd wrote: >> On 06/18, Chunyan Zhang wrote: >>> + kint = DIV_ROUND_CLOSEST(((fvco - refin * nint * CCU_PLL_1M)/10000) * >>> + ((mask >> (shift + i)) + 1), refin * 100) << i; >>> + cfg[index].val |= (kint << shift) & mask; >>> + cfg[index].msk |= mask; >>> + >>> + ibias_val = pll_get_ibias(fvco, pll->itable); >>> + >>> + mask = pmask(pll, PLL_IBIAS); >>> + index = pindex(pll, PLL_IBIAS); >>> + shift = pshift(pll, PLL_IBIAS); >>> + cfg[index].val |= ibias_val << shift & mask; >>> + cfg[index].msk |= mask; >>> + >>> + for (i = 0; i < reg_num; i++) { >>> + if (cfg[i].msk) >>> + ccu_pll_writel(pll, i, cfg[i].val, cfg[i].msk); >>> + } >>> + >> >> Are we waiting for the writel() to go through above? If so we >> need a readl() of the same register to make sure the write has >> completed before delaying. > > After writing these configuration registers, we have to wait a certain > time to make sure the pll has worked as we configured. This depends > on other circuit part, so we use udelay rather than reading the same > register. I think you have to do both: normally the writel() is not guaranteed to arrive at the device until you read back from an address in the same device, so the delay must happen after the readl(), or you won't know how long to wait for. Arnd