Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753168AbdFVLww (ORCPT ); Thu, 22 Jun 2017 07:52:52 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:47602 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753135AbdFVLwt (ORCPT ); Thu, 22 Jun 2017 07:52:49 -0400 Subject: Re: [PATCH 1/2] dt-bindings: spi: Document the STM32 SPI bindings To: Neil Armstrong , Mark Brown , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue CC: , , , References: <1498055526-6918-1-git-send-email-amelie.delaunay@st.com> <1498055526-6918-2-git-send-email-amelie.delaunay@st.com> <5df6d07a-59b7-6460-75c5-c3b239067616@baylibre.com> From: Amelie DELAUNAY Message-ID: Date: Thu, 22 Jun 2017 13:51:51 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <5df6d07a-59b7-6460-75c5-c3b239067616@baylibre.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG8NODE2.st.com (10.75.127.23) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-06-22_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4002 Lines: 111 On 06/21/2017 05:20 PM, Neil Armstrong wrote: > On 06/21/2017 04:32 PM, Amelie Delaunay wrote: >> This patch adds the documentation of device tree bindings >> for the STM32 SPI controller. >> >> Signed-off-by: Amelie Delaunay >> --- >> .../devicetree/bindings/spi/spi-stm32.txt | 60 ++++++++++++++++++++++ >> 1 file changed, 60 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/spi/spi-stm32.txt >> >> diff --git a/Documentation/devicetree/bindings/spi/spi-stm32.txt b/Documentation/devicetree/bindings/spi/spi-stm32.txt >> new file mode 100644 >> index 0000000..3958bf6 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/spi-stm32.txt >> @@ -0,0 +1,60 @@ >> +STMicroelectronics STM32 SPI Controller >> + >> +The STM32 SPI controller is used to communicate with external devices using >> +the Serial Peripheral Interface. It supports full-duplex, half-duplex and >> +simplex synchronous serial communication with external devices. It supports >> +from 4 to 32-bit data size. Although it can be configured as master or slave, >> +only master is supported by the driver. >> + >> +Required properties: >> +- compatible: Must be "st,stm32-spi". > > Hi Amelie, > > What about the gen1 SPI devices like the F4 ? > > It should have been better to use SoC specific compatible, or specify the SPI HW gen like gen1 or gen2. > > Neil > Hi Neil, The gen1 SPI controller embedded on F4/F7 is different from gen2 embedded on H7 and just to illustrate this, there are 5 main registers (16-bit) on gen1 versus 10 main registers on gen2 (32-bit)! Their operating modes are different, fifo management and so on... Moreover, I know that the community is working on an SPI driver for F4. I agree with you on the fact that it would be better to use a SoC specific compatible: I will send a v2 with "st,stm32h7-spi". This way, this will be aligned with what have been done for the I2S part of this controller: https://patchwork.kernel.org/patch/9737799/ By the way, I also noticed that my optional property "st,spi-midi-ns" doesn't fit with the example "st,spi-midi". I will fix that in the v2 and keep "st,spi-midi-ns". Regards, Amelie >> +- reg: Offset and length of the device's register set. >> +- interrupts: Must contain the interrupt id. >> +- clocks: Must contain an entry for spiclk (which feeds the internal clock >> + generator). >> +- #address-cells: Number of cells required to define a chip select address. >> +- #size-cells: Should be zero. >> + >> +Optional properties: >> +- resets: Must contain the phandle to the reset controller. >> +- A pinctrl state named "default" may be defined to set pins in mode of >> + operation for SPI transfer. >> +- dmas: DMA specifiers for tx and rx dma. DMA fifo mode must be used. See the >> + STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt. >> +- dma-names: DMA request names should include "tx" and "rx" if present. >> +- cs-gpios: list of GPIO chip selects. See the SPI bus bindings, >> + Documentation/devicetree/bindings/spi/spi-bus.txt >> + >> + >> +Child nodes represent devices on the SPI bus >> + See ../spi/spi-bus.txt >> + >> +Optional properties: >> +- st,spi-midi-ns: (Master Inter-Data Idleness) minimum time delay in >> + nanoseconds inserted between two consecutive data frames. >> + >> + >> +Example: >> + spi2: spi@40003800 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + compatible = "st,stm32-spi"; >> + reg = <0x40003800 0x400>; >> + interrupts = <36>; >> + clocks = <&rcc SPI2_CK>; >> + resets = <&rcc 1166>; >> + dmas = <&dmamux1 0 39 0x400 0x01>, >> + <&dmamux1 1 40 0x400 0x01>; >> + dma-names = "rx", "tx"; >> + pinctrl-0 = <&spi2_pins_b>; >> + pinctrl-names = "default"; >> + status = "okay"; >> + cs-gpios = <&gpioa 11 0>; >> + >> + spidev@0 { >> + compatible = "spidev"; >> + reg = <0>; >> + spi-max-frequency = <4000000>; >> + st,spi-midi = <4000>; >> + }; >> + }; >> >