Date: Thu, 22 Jun 2017 19:22:57 +0100
From: Will Deacon <will.deacon@arm.com>
To: Geetha sowjanya <gakula@caviumnetworks.com>
Cc: robin.murphy@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org,
        sudeep.holla@arm.com, iommu@lists.linux-foundation.org,
        robert.moore@intel.com, lv.zheng@intel.com, rjw@rjwysocki.net,
        jcm@redhat.com, linux-kernel@vger.kernel.org,
        robert.richter@cavium.com, catalin.marinas@arm.com,
        sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org,
        linux-acpi@vger.kernel.org, geethasowjanya.akula@gmail.com,
        devel@acpica.org, linu.cherian@cavium.com,
        Charles.Garcia-Tobin@arm.com, robh@kernel.org
Subject: Re: [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds
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On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote:
> Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas.
> 1. Errata ID #74
>    SMMU register alias Page 1 is not implemented
> 2. Errata ID #126
>    SMMU doesnt support unique IRQ lines and also MSI for gerror,
>    eventq and cmdq-sync
> 
> The following patchset does software workaround for these two erratas.

I've picked up the first two patches, and left comments on the final patch.

Will