Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753745AbdFVVug (ORCPT ); Thu, 22 Jun 2017 17:50:36 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:59666 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753557AbdFVVue (ORCPT ); Thu, 22 Jun 2017 17:50:34 -0400 From: Chris Packham To: =?iso-8859-1?Q?Jan_L=FCbbe?= CC: "bp@alien8.de" , "linux-arm-kernel@lists.infradead.org" , "linux-edac@vger.kernel.org" , Rob Herring , Mark Rutland , Russell King , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [RFC PATCH 3/4] ARM: l2x0: add arm,ecc-enable property for aurora Thread-Topic: [RFC PATCH 3/4] ARM: l2x0: add arm,ecc-enable property for aurora Thread-Index: AQHS4A1S9YoYe6o32kySMibpINKWBg== Date: Thu, 22 Jun 2017 21:50:29 +0000 Message-ID: References: <20170608041124.4624-1-chris.packham@alliedtelesis.co.nz> <20170608041124.4624-4-chris.packham@alliedtelesis.co.nz> <1496998692.3536.24.camel@pengutronix.de> <220533aeb8f64e829f483e38e209cdc8@svr-chch-ex1.atlnz.lc> <1498142790.2533.80.camel@pengutronix.de> Accept-Language: en-NZ, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [2001:df5:b000:22:17d:b43b:e662:49e3] Content-Type: text/plain; charset="iso-8859-1" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v5MLojIM018033 Content-Length: 2072 Lines: 44 On 23/06/17 02:46, Jan L?bbe wrote: > Chris, > > On So, 2017-06-11 at 22:55 +0000, Chris Packham wrote: >> On 09/06/17 20:58, Jan L?bbe wrote: >>> On Do, 2017-06-08 at 16:11 +1200, Chris Packham wrote: >>>> + if (of_property_read_bool(np, "arm,ecc-enable")) { >>>> + mask |= L2C_AUX_CTRL_EVTMON_ENABLE; >>>> + val |= L2C_AUX_CTRL_EVTMON_ENABLE; >>>> + } else if (of_property_read_bool(np, "arm,ecc-disable")) { >>>> + mask |= L2C_AUX_CTRL_EVTMON_ENABLE; >>>> + } >>> >>> Unless I misunderstand the code in __l2c_init(), the mask is used to >>> specify the bits to preserve: >>> old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); >>> aux &= aux_mask; >>> aux |= aux_val; >>> >>> if (old_aux != aux) >>> pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n", >>> old_aux, aux); >>> >>> So the arm,ecc-disable property will have no effect. This probably also >>> applies to patch 2/4. The existing property *-disable code removes the >>> corresponding bit from the mask. >> >> Indeed the disable version should be mask &= ~L2C_AUX_CTRL_EVTMON_ENABLE >> and I was probably a little lazy to have used the L2C EVTMON instead of >> adding AURORA specific ones like you have in your series. >> >> I'll rebase my series on top of yours and send it direct to you so you >> can include it in the overall submission. > > While picking up your arm,parity-enable and arm,ecc-enable patches for > my series, I noticed that the mask variable is inverted when merging the > local changes into aux_val/aux_mask at the end of aurora_of_parse. So I > now believe your code is correct. ;) I'd appreciate a close look, > nevertheless. For my part I tested the enable case but I never tested the disable case (because u-boot doesn't enable it there's nothing to disable). I can probably just poke the register before starting the kernel to confirm the disable case works with whatever masking logic we end up with.