Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753790AbdFVVzx (ORCPT ); Thu, 22 Jun 2017 17:55:53 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:53180 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751202AbdFVVzv (ORCPT ); Thu, 22 Jun 2017 17:55:51 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D4512602BC Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Thu, 22 Jun 2017 14:55:49 -0700 From: Stephen Boyd To: Sylwester Nawrocki Cc: Krzysztof Kozlowski , Michael Turquette , Kukjin Kim , Tomasz Figa , Chanwoo Choi , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Marek Szyprowski Subject: Re: [PATCH 1/2] clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLL Message-ID: <20170622215549.GM4493@codeaurora.org> References: <20170621190807.14850-1-krzk@kernel.org> <20170621190807.14850-2-krzk@kernel.org> <99de23b6-4049-7542-008b-abf65df356f0@samsung.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <99de23b6-4049-7542-008b-abf65df356f0@samsung.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1329 Lines: 32 On 06/22, Sylwester Nawrocki wrote: > On 06/21/2017 09:08 PM, Krzysztof Kozlowski wrote: > >Similarly to commit f1e9203e2366 ("clk: samsung: Fix Exynos 5420 pinctrl > >setup and clock disable failure due to domain being gated") for > >Exynos5420, the Exynos4412 also requires that EPLL is not disabled. > >Otherwise any access to MAUDIO block will silently halt. > > > >This was not visible before because EPLL on Exynos4 could not be > >disabled before commit 6edfa11cb396 ("clk: samsung: > >Add enable/disable operation for PLL36XX clocks"). After this commit, > >on Odroid U3 board one can see silent hang, usually with last (but > >unrelated) messages: > > > > [ 2.382741] input: gpio_keys as /devices/platform/gpio_keys/input/input0 > > [ 2.405686] usb 1-3: new high-speed USB device number 3 using exynos-ehci > > [ 2.419843] max77686-rtc max77686-rtc: setting system clock to 2017-06-21 17:04:13 UTC (1498064653) > > > >Mark Exynos4 variant as also needed EPLL to be enabled all the time. > > > >Signed-off-by: Krzysztof Kozlowski > Reviewed-by: Sylwester Nawrocki > > Stephen, Mike, > > Can you please apply this patch directly? > Applied to clk-next. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project