Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754047AbdFWBLy (ORCPT ); Thu, 22 Jun 2017 21:11:54 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:8818 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752832AbdFWBLw (ORCPT ); Thu, 22 Jun 2017 21:11:52 -0400 Subject: Re: [PATCH v2 2/5] dt-bindings: scsi: ufs: add document for hi3660-ufs To: Subhash Jadavani , Arnd Bergmann References: <20170616065119.10704-1-butao@hisilicon.com> <20170616065119.10704-3-butao@hisilicon.com> <0f79aeea-53e3-6bea-ffa6-0e057f2ff83b@huawei.com> <5c4c0a7b844055b32b8463fcee04401e@codeaurora.org> CC: Rob Herring , Mark Rutland , "Wei Xu" , Catalin Marinas , "Will Deacon" , Vinayak Holikatti , "James E.J. Bottomley" , "Martin K. Petersen" , Kevin Hilman , "Gregory CLEMENT" , Thomas Petazzoni , Masahiro Yamada , Riku Voipio , Thierry Reding , Krzysztof Kozlowski , Eric Anholt , , "Linux Kernel Mailing List" , Linux ARM , , "Guodong Xu" , , , From: Bu Tao Message-ID: Date: Fri, 23 Jun 2017 09:09:54 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <5c4c0a7b844055b32b8463fcee04401e@codeaurora.org> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.142.51.208] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.594C6A7A.00D7,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 1f99031b066954e34c611c7a0a653a6d Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2697 Lines: 66 在 2017/6/23 9:05, Subhash Jadavani 写道: > On 2017-06-22 04:51, Arnd Bergmann wrote: >> On Thu, Jun 22, 2017 at 1:44 PM, Bu Tao wrote: >>> 在 2017/6/17 5:51, Arnd Bergmann 写道: >>>> On Fri, Jun 16, 2017 at 8:51 AM, Bu Tao wrote: >>>>> +Optional properties for board device: >>>>> +- ufs-hi3660-use-rate-B : specifies UFS rate-B >>>>> +- ufs-hi3660-broken-fastauto : specifies no fastauto >>>>> +- ufs-hi3660-use-HS-GEAR3 : specifies UFS HS-GEAR3 >>>>> +- ufs-hi3660-use-HS-GEAR2 : specifies UFS HS-GEAR2 >>>>> +- ufs-hi3660-use-HS-GEAR1 : specifies UFS HS-GEAR1 >>>>> +- ufs-hi3660-broken-clk-gate-bypass : specifies no clk-gate >>>>> +- ufs-hi3660-use-one-line : specifies UFS use one line work >>>>> +- reset-gpio : specifies to reset devices >>>> >>>> >>>> Some of these sound rather generic and might apply to UFS >>>> implementations >>>> other than hi3660, so I'd suggest adding them to the base ufs >>>> binding with >>>> a generic name instead. >>>> >>>> Any DT properties that might be useful across multiple implementations >>>> should be parsed in generic code that gets called by the individual >>>> drivers, >>>> and then the properties that are specific to the integration work >>>> done by >>>> hisilicon should be prefixed with "hisilicon,", but not normally >>>> with the >>>> SoC name: it is quite possible that another SoC will be derived from >>>> this >>>> chip and it should reuse the properties. >>> >>> >>> I do not know wheher other SoC need to use the optional properties as >>> abover. So here the name of the optional properties has "hi3660". >> >> They should not have "hi3660" in their names either way, independent >> of where they are used. > > > Yes, i agree with Arnd that SoCs might also need these so please make > these properties generic (put them under > Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt) and also move > their parsing code in generic driver (ufshcd.c or ufshcd-pltfrm.c). > Thanks for your comments. I will modify this and update soon. >> >>>> (note: this is different from the value of the "compatible" property >>>> that >>>> is meant to be as specific as possible". >>>> >>>> Also, please clarify how your binding relates to the ufshcd binding >>>> in Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt: does >>>> hi3660 implement any registers that are shared with ufshcd, or does >>>> it use the same physical interface with a different register set? >>> >>> No, only show how to use the dt-binding for hi3660 SoC >> >> My question was about the hardware: does hi3660 implement ufshcd >> or not? >> >> Arnd >