Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754199AbdFWDJx (ORCPT ); Thu, 22 Jun 2017 23:09:53 -0400 Received: from mail.kernel.org ([198.145.29.99]:33502 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754089AbdFWDJw (ORCPT ); Thu, 22 Jun 2017 23:09:52 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 43B80217C5 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=luto@kernel.org MIME-Version: 1.0 In-Reply-To: References: From: Andy Lutomirski Date: Thu, 22 Jun 2017 20:09:29 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID To: Thomas Gleixner Cc: Andy Lutomirski , X86 ML , "linux-kernel@vger.kernel.org" , Borislav Petkov , Linus Torvalds , Andrew Morton , Mel Gorman , "linux-mm@kvack.org" , Nadav Amit , Rik van Riel , Dave Hansen , Arjan van de Ven , Peter Zijlstra Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1405 Lines: 27 On Thu, Jun 22, 2017 at 2:22 PM, Thomas Gleixner wrote: > On Thu, 22 Jun 2017, Andy Lutomirski wrote: >> On Thu, Jun 22, 2017 at 5:21 AM, Thomas Gleixner wrote: >> > Now one other optimization which should be trivial to add is to keep the 4 >> > asid context entries in cpu_tlbstate and cache the last asid in thread >> > info. If that's still valid then use it otherwise unconditionally get a new >> > one. That avoids the whole loop machinery and thread info is cache hot in >> > the context switch anyway. Delta patch on top of your version below. >> >> I'm not sure I understand. If an mm has ASID 0 on CPU 0 and ASID 1 on >> CPU 1 and a thread in that mm bounces back and forth between those >> CPUs, won't your patch cause it to flush every time? > > Yeah, I was too focussed on the non migratory case, where two tasks from > different processes play rapid ping pong. That's what I was looking at for > various reasons. > > There the cached asid really helps by avoiding the loop completely, but > yes, the search needs to be done for the bouncing between CPUs case. > > So maybe a combo of those might be interesting. > I'm not too worried about optimizing away the loop. It's a loop over four or six things that are all in cachelines that we need anyway. I suspect that we'll never be able to see it in any microbenchmark, let alone real application.