Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754376AbdFWFJI (ORCPT ); Fri, 23 Jun 2017 01:09:08 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:16857 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751409AbdFWFJF (ORCPT ); Fri, 23 Jun 2017 01:09:05 -0400 From: Zhi Mao To: , Thierry Reding , Rob Herring , Mark Rutland , Matthias Brugger , CC: , , , , , , , , , Subject: [PATCH v2 0/6] mediatek: pwm driver add MT2712/MT7622 support Date: Fri, 23 Jun 2017 13:08:19 +0800 Message-ID: <1498194505-30930-1-git-send-email-zhi.mao@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 813 Lines: 19 change in v2: 1. add error check for enable colock control flow 2. use "goto err_clk(main/top)" coding style, for preparing clk error case 3. remove comments inline /*===*/ 4. move "PWM_CLK_DIV_MAX" modification to its own patch 5. move pwm source clock selection to its own patch Zhi Mao (6): pwm: kconfig: modify mediatek information pwm: mediatek: fix pwm source clock selection pwm: mediatek: fix clock control issue pwm: bindings: add MT2712/MT7622 information pwm: mediatek: add PWM_CLK_DIV_MAX pwm: mediatek: add MT2712/MT7622 support .../devicetree/bindings/pwm/pwm-mediatek.txt | 6 +- drivers/pwm/Kconfig | 2 +- drivers/pwm/pwm-mediatek.c | 132 ++++++++++++++------ 3 files changed, 103 insertions(+), 37 deletions(-)