Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754441AbdFWP23 (ORCPT ); Fri, 23 Jun 2017 11:28:29 -0400 Received: from mail.kernel.org ([198.145.29.99]:49692 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753862AbdFWP21 (ORCPT ); Fri, 23 Jun 2017 11:28:27 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 96C7022B66 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=luto@kernel.org MIME-Version: 1.0 In-Reply-To: <20170623115026.qqy5mpyihymocaet@pd.tnic> References: <57c1d18b1c11f9bc9a3bcf8bdee38033415e1a13.1498022414.git.luto@kernel.org> <20170623115026.qqy5mpyihymocaet@pd.tnic> From: Andy Lutomirski Date: Fri, 23 Jun 2017 08:28:05 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 10/11] x86/mm: Enable CR4.PCIDE on supported systems To: Borislav Petkov Cc: Andy Lutomirski , X86 ML , "linux-kernel@vger.kernel.org" , Linus Torvalds , Andrew Morton , Mel Gorman , "linux-mm@kvack.org" , Nadav Amit , Rik van Riel , Dave Hansen , Arjan van de Ven , Peter Zijlstra , Juergen Gross , Boris Ostrovsky Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2847 Lines: 72 On Fri, Jun 23, 2017 at 4:50 AM, Borislav Petkov wrote: > On Tue, Jun 20, 2017 at 10:22:16PM -0700, Andy Lutomirski wrote: >> We can use PCID if the CPU has PCID and PGE and we're not on Xen. >> >> By itself, this has no effect. The next patch will start using >> PCID. >> >> Cc: Juergen Gross >> Cc: Boris Ostrovsky >> Signed-off-by: Andy Lutomirski >> --- >> arch/x86/include/asm/tlbflush.h | 8 ++++++++ >> arch/x86/kernel/cpu/common.c | 15 +++++++++++++++ >> arch/x86/xen/enlighten_pv.c | 6 ++++++ >> 3 files changed, 29 insertions(+) >> >> diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h >> index 87b13e51e867..57b305e13c4c 100644 >> --- a/arch/x86/include/asm/tlbflush.h >> +++ b/arch/x86/include/asm/tlbflush.h >> @@ -243,6 +243,14 @@ static inline void __flush_tlb_all(void) >> __flush_tlb_global(); >> else >> __flush_tlb(); >> + >> + /* >> + * Note: if we somehow had PCID but not PGE, then this wouldn't work -- >> + * we'd end up flushing kernel translations for the current ASID but >> + * we might fail to flush kernel translations for other cached ASIDs. >> + * >> + * To avoid this issue, we force PCID off if PGE is off. >> + */ >> } >> >> static inline void __flush_tlb_one(unsigned long addr) >> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c >> index 904485e7b230..01caf66b270f 100644 >> --- a/arch/x86/kernel/cpu/common.c >> +++ b/arch/x86/kernel/cpu/common.c >> @@ -1143,6 +1143,21 @@ static void identify_cpu(struct cpuinfo_x86 *c) >> setup_smep(c); >> setup_smap(c); >> >> + /* Set up PCID */ >> + if (cpu_has(c, X86_FEATURE_PCID)) { >> + if (cpu_has(c, X86_FEATURE_PGE)) { > > What are we protecting ourselves here against? Funny virtualization guests? > > Because PGE should be ubiquitous by now. Or have you heard something? Yes, funny VM guests. I've been known to throw weird options at qemu myself, and I prefer when the system works. In this particular case, I think the failure mode would be stale kernel TLB entries, and that would be really annoying. > >> + cr4_set_bits(X86_CR4_PCIDE); >> + } else { >> + /* >> + * flush_tlb_all(), as currently implemented, won't >> + * work if PCID is on but PGE is not. Since that >> + * combination doesn't exist on real hardware, there's >> + * no reason to try to fully support it. >> + */ >> + clear_cpu_cap(c, X86_FEATURE_PCID); >> + } >> + } > > This whole in setup_pcid() I guess, like the rest of the features. Done.