Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751414AbdFYRBE (ORCPT ); Sun, 25 Jun 2017 13:01:04 -0400 Received: from mx2.suse.de ([195.135.220.15]:57287 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751353AbdFYRAi (ORCPT ); Sun, 25 Jun 2017 13:00:38 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Masahiro Yamada , Satoru OKAMOTO , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rob Herring , Mark Rutland , Russell King , devicetree@vger.kernel.org Subject: [PATCH 5/5] ARM: dts: mb86s71-f-cue: Add fake UART0 clock Date: Sun, 25 Jun 2017 19:00:20 +0200 Message-Id: <20170625170020.11791-6-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170625170020.11791-1-afaerber@suse.de> References: <20170625170020.11791-1-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 766 Lines: 33 As long as the clk driver is not building, use a fixed-clock for the UART. Signed-off-by: Andreas Färber --- arch/arm/boot/dts/mb86s71-f-cue.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mb86s71-f-cue.dts b/arch/arm/boot/dts/mb86s71-f-cue.dts index 148d1aee11a6..726bf189e8e7 100644 --- a/arch/arm/boot/dts/mb86s71-f-cue.dts +++ b/arch/arm/boot/dts/mb86s71-f-cue.dts @@ -27,6 +27,12 @@ device_type = "memory"; reg = <0x80000000 0x80000000>; }; + + uart0_clk: uart0-clk { + compatible = "fixed-clock"; + clock-frequency = <7813000>; + #clock-cells = <0>; + }; }; &arch_timer { @@ -35,4 +41,6 @@ &uart0 { status = "okay"; + clocks = <&uart0_clk>; + clock-names = "apb_pclk"; }; -- 2.12.3