Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751440AbdFYRBT (ORCPT ); Sun, 25 Jun 2017 13:01:19 -0400 Received: from mx2.suse.de ([195.135.220.15]:57281 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751208AbdFYRAi (ORCPT ); Sun, 25 Jun 2017 13:00:38 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Masahiro Yamada , Satoru OKAMOTO , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rob Herring , Mark Rutland , Russell King , devicetree@vger.kernel.org Subject: [PATCH 4/5] ARM: dts: Add Socionext MB86S71 and Fujitsu F-Cue Date: Sun, 25 Jun 2017 19:00:19 +0200 Message-Id: <20170625170020.11791-5-afaerber@suse.de> X-Mailer: git-send-email 2.12.3 In-Reply-To: <20170625170020.11791-1-afaerber@suse.de> References: <20170625170020.11791-1-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 6237 Lines: 254 Add Device Trees for Socionext MB86S71 SoC and Fujitsu F-Cue board. Signed-off-by: Andreas Färber --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/mb86s71-f-cue.dts | 38 ++++++++ arch/arm/boot/dts/mb86s71.dtsi | 178 ++++++++++++++++++++++++++++++++++++ 3 files changed, 218 insertions(+) create mode 100644 arch/arm/boot/dts/mb86s71-f-cue.dts create mode 100644 arch/arm/boot/dts/mb86s71.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4b17f35dc9a7..48dda2de0a3d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -526,6 +526,8 @@ dtb-$(CONFIG_ARCH_MXS) += \ imx28-m28evk.dtb \ imx28-sps1.dtb \ imx28-tx28.dtb +dtb-$(CONFIG_ARCH_MB86S7X) += \ + mb86s71-f-cue.dtb dtb-$(CONFIG_ARCH_NOMADIK) += \ ste-nomadik-s8815.dtb \ ste-nomadik-nhk15.dtb diff --git a/arch/arm/boot/dts/mb86s71-f-cue.dts b/arch/arm/boot/dts/mb86s71-f-cue.dts new file mode 100644 index 000000000000..148d1aee11a6 --- /dev/null +++ b/arch/arm/boot/dts/mb86s71-f-cue.dts @@ -0,0 +1,38 @@ +/* + * Fujitsu F-Cue board + * + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "mb86s71.dtsi" + +/ { + compatible = "fujitsu,f-cue", "fujitsu,mb86s71"; + model = "Fujitsu F-Cue"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* vendor U-Boot looks for /memory */ + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; +}; + +&arch_timer { + clock-frequency = <125000000>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mb86s71.dtsi b/arch/arm/boot/dts/mb86s71.dtsi new file mode 100644 index 000000000000..154f1ab89f0a --- /dev/null +++ b/arch/arm/boot/dts/mb86s71.dtsi @@ -0,0 +1,178 @@ +/* + * Socionext MB86S71 SoC + * + * Copyright (c) 2017 Andreas Färber + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#include + +/ { + compatible = "fujitsu,mb86s71"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x0>; + cci-control-port = <&cci_control4>; + next-level-cache = <&l2_big>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x1>; + cci-control-port = <&cci_control4>; + next-level-cache = <&l2_big>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + cci-control-port = <&cci_control3>; + next-level-cache = <&l2_little>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + cci-control-port = <&cci_control3>; + next-level-cache = <&l2_little>; + }; + + l2_big: l2-cache-big { + compatible = "cache"; + }; + + l2_little: l2-cache-little { + compatible = "cache"; + }; + }; + + arch_timer: timer { + compatible = "arm,armv7-timer"; + interrupts = , + ; + }; + + pmu-big { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + pmu-little { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu2>, <&cpu3>; + }; + + cci@2c090000 { + compatible = "arm,cci-400"; + reg = <0x2c090000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2c090000 0x10000>; + + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + reg = <0x1000 0x1000>; + interface-type = "ace-lite"; + }; + + cci_control1: slave-if@2000 { + compatible = "arm,cci-400-ctrl-if"; + reg = <0x2000 0x1000>; + interface-type = "ace-lite"; + }; + + cci_control2: slave-if@3000 { + compatible = "arm,cci-400-ctrl-if"; + reg = <0x3000 0x1000>; + interface-type = "ace-lite"; + }; + + cci_control3: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + reg = <0x4000 0x1000>; + interface-type = "ace"; + }; + + cci_control4: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + reg = <0x5000 0x1000>; + interface-type = "ace"; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r0"; + reg = <0x9000 0x5000>; + interrupts = , + , + , + , + ; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x80000000>; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic"; + reg = <0x2c001000 0x1000>, + <0x2c002000 0x2000>, + <0x2c004000 0x2000>, + <0x2c006000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + uart0: serial@31040000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x31040000 0x100>; + arm,primecell-periphid = <0x00341011>; + interrupts = ; + status = "disabled"; + }; + + uart1: serial@31050000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x31050000 0x100>; + arm,primecell-periphid = <0x00341011>; + interrupts = ; + status = "disabled"; + }; + + uart2: serial@31060000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x31060000 0x100>; + arm,primecell-periphid = <0x00341011>; + interrupts = ; + status = "disabled"; + }; + + timer@31080000 { + compatible = "arm,sp804"; + reg = <0x31080000 0x10000>; + interrupts = , + ; + }; + }; +}; -- 2.12.3