Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751895AbdFZMmy (ORCPT ); Mon, 26 Jun 2017 08:42:54 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:36659 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751489AbdFZMmn (ORCPT ); Mon, 26 Jun 2017 08:42:43 -0400 From: Jonathan Liu To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland , Russell King Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Jonathan Liu Subject: [PATCH] ARM: dts: sun7i: Add A20 LCD0 RGB888 pins Date: Mon, 26 Jun 2017 22:42:49 +1000 Message-Id: <20170626124249.9475-1-net147@gmail.com> X-Mailer: git-send-email 2.13.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 967 Lines: 32 The LCD0 controller on the A20 can do RGB output up to 8 bits per channel. Add the pins for RGB888 output. Signed-off-by: Jonathan Liu --- arch/arm/boot/dts/sun7i-a20.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 96bee776e145..09a0e89bed11 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1183,6 +1183,17 @@ function = "ir1"; }; + lcd0_rgb888_pins: lcd0_rgb888@0 { + allwinner,pins = "PD0", "PD1", "PD2", "PD3", + "PD4", "PD5", "PD6", "PD7", + "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + allwinner,function = "lcd0"; + }; + mmc0_pins_a: mmc0@0 { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; -- 2.13.1