Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752963AbdF0R6C (ORCPT ); Tue, 27 Jun 2017 13:58:02 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:33964 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751974AbdF0R54 (ORCPT ); Tue, 27 Jun 2017 13:57:56 -0400 Subject: Re: [PATCH 2/3] mtd: spi-nor: core code for the Altera Quadspi Flash Controller v2 To: matthew.gerlach@linux.intel.com References: <1498493619-4633-1-git-send-email-matthew.gerlach@linux.intel.com> <1498493619-4633-3-git-send-email-matthew.gerlach@linux.intel.com> <852b819d-ea7a-4854-cae1-3857cf92930d@gmail.com> <0cb464ef-eeb8-ebc9-fde9-b6d42bf03877@gmail.com> Cc: vndao@altera.com, dwmw2@infradead.org, computersforpeace@gmail.com, boris.brezillon@free-electrons.com, richard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org, mark.rutland@arm.com, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, davem@davemloft.net, mchehab@kernel.org From: Marek Vasut Message-ID: <9ca626e3-fc80-2b50-85aa-5db102dc9b7f@gmail.com> Date: Tue, 27 Jun 2017 19:55:36 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1823 Lines: 49 On 06/27/2017 07:26 PM, matthew.gerlach@linux.intel.com wrote: [...] >>>>> +#ifndef __ALTERA_QUADSPI_H >>>>> +#define __ALTERA_QUADSPI_H >>>>> + >>>>> +#include >>>>> + >>>>> +#define ALTERA_QUADSPI_FL_BITREV_READ BIT(0) >>>>> +#define ALTERA_QUADSPI_FL_BITREV_WRITE BIT(1) >>>>> + >>>>> +#define ALTERA_QUADSPI_MAX_NUM_FLASH_CHIP 3 >>>>> + >>>>> +int altera_quadspi_create(struct device *dev, void __iomem *csr_base, >>>>> + void __iomem *data_base, void __iomem *window_reg, >>>>> + size_t window_size, u32 flags); >>>>> + >>>>> +int altera_qspi_add_bank(struct device *dev, >>>>> + u32 bank, struct device_node *np); >>>>> + >>>>> +int altera_quadspi_remove_banks(struct device *dev); >>>> >>>> Why is this header needed at all ? >>> >>> This header is needed because of the very different ways >>> FPGAs can be used with a processor running Linux. In the case of a >>> soft processor in the FPGA or an ARM connected to a FPGA, this header >>> is not necessary because device trees are used to probe the driver. >>> However, if the FPGA is on a PCIe card connected to an x86, device trees >>> are not generally used, and the pcie driver must enumerate the >>> "sub-driver". >> >> But we don't support that later part, do we ? > > There is currently v2 patch set for the intel-fpga PCIe driver being > reviewed where I am adding support for version 2 of the Altera Quadspi > controller. It'd be real nice to mention that in the cover letter with a link to that patchset , otherwise it's real hard to understand why you did this. > This technique of separating core driver code from platform/device tree > code has been reviewed and accepted for the Altera Partial > Reconfiguration IP, Altera Freeze Bridge, and the fpga region. -- Best regards, Marek Vasut