Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751953AbdF1OdB (ORCPT ); Wed, 28 Jun 2017 10:33:01 -0400 Received: from mga02.intel.com ([134.134.136.20]:36717 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751695AbdF1Ocy (ORCPT ); Wed, 28 Jun 2017 10:32:54 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,275,1496127600"; d="scan'208";a="1188020948" From: kan.liang@intel.com To: acme@kernel.org, linux-kernel@vger.kernel.org Cc: mingo@redhat.com, peterz@infradead.org, jolsa@redhat.com, adrian.hunter@intel.com, alexander.shishkin@linux.intel.com, ak@linux.intel.com, Kan Liang Subject: [PATCH] perf tools: set no branch type for dummy event in PT Date: Wed, 28 Jun 2017 10:31:53 -0400 Message-Id: <20170628143153.29643-1-kan.liang@intel.com> X-Mailer: git-send-email 2.9.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2186 Lines: 67 From: Kan Liang An earlier kernel patch allowed enabling PT and LBR at the same time on Goldmont. commit ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") However, users still cannot use Intel PT and LBRs simultaneously. $ sudo perf record -e cycles,intel_pt//u -b -- sleep 1 Error: PMU Hardware doesn't support sampling/overflow-interrupts. PT implicitly adds dummy event in perf tool. dummy event is software event which doesn't support LBR. Always setting branch_type=no for dummy event in Intel PT. Signed-off-by: Kan Liang --- tools/perf/arch/x86/util/intel-pt.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index f630de0..651ab9e 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -544,6 +544,22 @@ static int intel_pt_validate_config(struct perf_pmu *intel_pt_pmu, evsel->attr.config); } +static int add_no_lbr_config_term(struct list_head *config_terms) +{ + struct perf_evsel_config_term *lbr_term; + + lbr_term = zalloc(sizeof(*lbr_term)); + if (!lbr_term) + return -ENOMEM; + + INIT_LIST_HEAD(&lbr_term->list); + lbr_term->type = PERF_EVSEL__CONFIG_TERM_BRANCH; + lbr_term->val.branch = strdup("no"); + list_add_tail(&lbr_term->list, config_terms); + + return 0; +} + static int intel_pt_recording_options(struct auxtrace_record *itr, struct perf_evlist *evlist, struct record_opts *opts) @@ -701,6 +717,8 @@ static int intel_pt_recording_options(struct auxtrace_record *itr, perf_evsel__set_sample_bit(switch_evsel, TIME); perf_evsel__set_sample_bit(switch_evsel, CPU); + add_no_lbr_config_term(&switch_evsel->config_terms); + opts->record_switch_events = false; ptr->have_sched_switch = 3; } else { @@ -760,6 +778,7 @@ static int intel_pt_recording_options(struct auxtrace_record *itr, /* And the CPU for switch events */ perf_evsel__set_sample_bit(tracking_evsel, CPU); } + add_no_lbr_config_term(&tracking_evsel->config_terms); } /* -- 2.9.4