Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753807AbdF2VsC (ORCPT ); Thu, 29 Jun 2017 17:48:02 -0400 Received: from mail-it0-f68.google.com ([209.85.214.68]:36720 "EHLO mail-it0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752728AbdF2VsA (ORCPT ); Thu, 29 Jun 2017 17:48:00 -0400 Date: Thu, 29 Jun 2017 16:47:58 -0500 From: Rob Herring To: Quentin Schulz Cc: mturquette@baylibre.com, sboyd@codeaurora.org, mark.rutland@arm.com, nicolas.ferre@microchip.com, alexandre.belloni@free-electrons.com, linux@armlinux.org.uk, boris.brezillon@free-electrons.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, Nicolas Ferre , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, alsa-devel@alsa-project.org, thomas.petazzoni@free-electrons.com Subject: Re: [PATCH 2/6] clk: at91: add audio pll clock driver Message-ID: <20170629214758.7a55wtssikekjjh4@rob-hp-laptop> References: <20170623090059.8371-1-quentin.schulz@free-electrons.com> <20170623090059.8371-3-quentin.schulz@free-electrons.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170623090059.8371-3-quentin.schulz@free-electrons.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1735 Lines: 35 On Fri, Jun 23, 2017 at 11:00:55AM +0200, Quentin Schulz wrote: > From: Nicolas Ferre > > This new clock driver set allows to have a fractional divided clock that > would generate a precise clock particularly suitable for audio > applications. > > The main audio pll clock has two children clocks: one that is connected > to the PMC, the other that can directly drive a pad. As these two routes > have different enable bits and different dividers and divider formula, > they are handled by two different drivers. Each of them could modify the > rate of the main audio pll parent. > The main audio pll clock can output 620MHz to 700MHz. > > Signed-off-by: Nicolas Ferre > Signed-off-by: Quentin Schulz > --- > .../devicetree/bindings/clock/at91-clock.txt | 10 + It would be nice to see at91 to transition away from a node per clock to just clock controller nodes. In any case: Acked-by: Rob Herring > arch/arm/mach-at91/Kconfig | 4 + > drivers/clk/at91/Makefile | 2 + > drivers/clk/at91/clk-audio-pll-pad.c | 204 ++++++++++++++++++ > drivers/clk/at91/clk-audio-pll-pmc.c | 175 +++++++++++++++ > drivers/clk/at91/clk-audio-pll.c | 237 +++++++++++++++++++++ > include/linux/clk/at91_pmc.h | 25 +++ > sound/soc/atmel/atmel-classd.c | 20 +- > 8 files changed, 658 insertions(+), 19 deletions(-) > create mode 100644 drivers/clk/at91/clk-audio-pll-pad.c > create mode 100644 drivers/clk/at91/clk-audio-pll-pmc.c > create mode 100644 drivers/clk/at91/clk-audio-pll.c