Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751793AbdGAE7E (ORCPT ); Sat, 1 Jul 2017 00:59:04 -0400 Received: from mailgw.actions.com.cn ([58.254.217.121]:61535 "EHLO mailgw.actions.com.cn" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751123AbdGAE7D (ORCPT ); Sat, 1 Jul 2017 00:59:03 -0400 X-Greylist: delayed 961 seconds by postgrey-1.27 at vger.kernel.org; Sat, 01 Jul 2017 00:59:02 EDT x-mimeole: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Subject: =?utf-8?B?562U5aSNOiBbUEFUQ0ggdjQgMjAvMjhdIEFSTTogb3dsOiBJ?= =?utf-8?B?bXBsZW1lbnQgQ1BVIGVuYWJsZS1tZXRob2QgZm9yIFM=?= =?utf-8?B?NTAw?= Date: Sat, 1 Jul 2017 12:42:56 +0800 Message-ID: In-Reply-To: <6d9d0d63-113e-b050-a54e-62746ebc6013@suse.de> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500 Thread-Index: AdLw653mo/rqduIcTceopz7K6nka0wBMFvzw References: <20170606005426.26446-1-afaerber@suse.de> <20170606005426.26446-21-afaerber@suse.de> <6d9d0d63-113e-b050-a54e-62746ebc6013@suse.de> From: =?utf-8?B?5YiY54Kc?= To: =?utf-8?B?QW5kcmVhcyBGw6RyYmVy?= , "Arnd Bergmann" , "Thomas Liau" Cc: "Linux ARM" , "mp-cs" , =?utf-8?B?5byg5Lic6aOO?= , =?utf-8?B?5byg5aSp55uK?= , <96boards@ucrobotics.com>, , "Linux Kernel Mailing List" , "Russell King" X-OriginalArrivalTime: 01 Jul 2017 04:42:57.0797 (UTC) FILETIME=[8303BB50:01D2F224] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v614xB0l002952 Content-Length: 2821 Lines: 74 Hi, Andrea OWL_CPUx_ADDR is the physical address of CPUx wakeup function. OWL_CPUx_FLAG is a valid flag of OWL_CPUx_ADDR. After CPUxs are wakeuped by SEV instruction, they will check their own OWL_CPUx_FLAG register. If the register vlaue is 0x55aa, CPUx will jump to OWL_CPUx_ADDR to boot up, otherwize go to sleep by WFE. So the pen release staff is not necessary, you can remove these code safely. BTW: CPU2/3 must exit the power gate state before wakeup, and CPU1 is always power on and has no power gate control. Best Regards, David Liu -----邮件原件----- 发件人: Andreas Färber [mailto:afaerber@suse.de] 发送时间: 2017年6月29日 23:22 收件人: Arnd Bergmann; Thomas Liau 抄送: Linux ARM; mp-cs; 张东风; 刘炜; 张天益; 96boards@ucrobotics.com; support@lemaker.org; Linux Kernel Mailing List; Russell King 主题: Re: [PATCH v4 20/28] ARM: owl: Implement CPU enable-method for S500 Am 29.06.2017 um 17:07 schrieb Arnd Bergmann: >>> +static int s500_smp_boot_secondary(unsigned int cpu, struct >>> +task_struct *idle) { >>> + unsigned long timeout; >>> + int ret; >>> + >>> + ret = s500_wakeup_secondary(cpu); >>> + if (ret) >>> + return ret; >>> + >>> + udelay(10); >>> + >>> + spin_lock(&boot_lock); >>> + >>> + /* >>> + * The secondary processor is waiting to be released from >>> + * the holding pen - release it, then wait for it to flag >>> + * that it has been released by resetting pen_release. >>> + */ >>> + write_pen_release(cpu_logical_map(cpu)); >>> + smp_send_reschedule(cpu); >>> + >>> + timeout = jiffies + (1 * HZ); >>> + while (time_before(jiffies, timeout)) { >>> + if (pen_release == -1) >>> + break; >>> + } >>> + >>> + writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); >>> + writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); >>> + >>> + spin_unlock(&boot_lock); >>> + >>> + return pen_release != -1 ? -ENOSYS : 0; } >> >> This looks more complicated than necessary. Why do you need the >> holding pen when you have a register to start up the CPU? >> > > It seems you missed my question here. Can you please follow up, and if > possible send a patch to remove the pen_release logic that appears to > be unnecessary here? I do not have any documentation on these registers, only the downstream code that I forward-ported here. If you tell me what you mean exactly, I can do some testing and if it still works submit a patch to simplify it. Comments from the so far quiet Actions Semi side would help, too. Regards, Andreas -- SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer, Jane Smithard, Graham Norton HRB 21284 (AG Nürnberg)