Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751875AbdGBNnK (ORCPT ); Sun, 2 Jul 2017 09:43:10 -0400 Received: from mail-ua0-f182.google.com ([209.85.217.182]:35278 "EHLO mail-ua0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751608AbdGBNnH (ORCPT ); Sun, 2 Jul 2017 09:43:07 -0400 MIME-Version: 1.0 In-Reply-To: <20170630134337.18245-1-romain.perier@collabora.com> References: <20170630134337.18245-1-romain.perier@collabora.com> From: Fabio Estevam Date: Sun, 2 Jul 2017 10:43:06 -0300 Message-ID: Subject: Re: [PATCH] ARM: dts: imx: Correct B850v3 clock assignment To: Romain Perier Cc: Shawn Guo , Sascha Hauer , Fabio Estevam , "devicetree@vger.kernel.org" , Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala , "linux-arm-kernel@lists.infradead.org" , linux-kernel , Martyn Welch Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 744 Lines: 17 On Fri, Jun 30, 2017 at 10:43 AM, Romain Perier wrote: > From: Martyn Welch > > The IPU that drives HDMI must have its pre_sel set to pll2_pfd_396m > to avoid stepping on the LVDS output's toes, as the PLL can't be clocked > to the pixel clock and to the LVDS serial clock (3.5*pixel clock) at the > same time. > > As we are using ipu1_di0 and ipu2_di0, ensure both are switched to > to pll2_pfd2_396m to avoid issues. The LDB driver will switch the > required IPU to ldb_di1 when it uses it to drive LVDS. > > Signed-off-by: Martyn Welch > Signed-off-by: Romain Perier Reviewed-by: Fabio Estevam