Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752549AbdGBQbs (ORCPT ); Sun, 2 Jul 2017 12:31:48 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:41940 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752243AbdGBQaj (ORCPT ); Sun, 2 Jul 2017 12:30:39 -0400 From: Paul Cercueil To: Ralf Baechle , Michael Turquette , Stephen Boyd , Rob Herring Cc: Paul Burton , Maarten ter Huurne , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux-clk@vger.kernel.org Subject: [PATCH v3 15/18] MIPS: JZ4770: Work around config2 misreporting associativity Date: Sun, 2 Jul 2017 18:30:13 +0200 Message-Id: <20170702163016.6714-16-paul@crapouillou.net> In-Reply-To: <20170702163016.6714-1-paul@crapouillou.net> References: <20170607200439.24450-2-paul@crapouillou.net> <20170702163016.6714-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1124 Lines: 43 From: Maarten ter Huurne According to config2, the associativity would be 5-ways, but the documentation states 4-ways, which also matches the documented L2 cache size of 256 kB. Signed-off-by: Maarten ter Huurne --- arch/mips/mm/sc-mips.c | 9 +++++++++ 1 file changed, 9 insertions(+) v2: No change v3: No change diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index c909c3342729..67a3b4d88580 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -15,6 +15,7 @@ #include #include #include +#include /* * MIPS32/MIPS64 L2 cache handling @@ -228,6 +229,14 @@ static inline int __init mips_sc_probe(void) else return 0; + /* + * According to config2 it would be 5-ways, but that is contradicted + * by all documentation. + */ + if (current_cpu_type() == CPU_JZRISC && + mips_machtype == MACH_INGENIC_JZ4770) + c->scache.ways = 4; + c->scache.waysize = c->scache.sets * c->scache.linesz; c->scache.waybit = __ffs(c->scache.waysize); -- 2.11.0