Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752420AbdGBQeS (ORCPT ); Sun, 2 Jul 2017 12:34:18 -0400 Received: from outils.crapouillou.net ([89.234.176.41]:38330 "EHLO crapouillou.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751717AbdGBQa0 (ORCPT ); Sun, 2 Jul 2017 12:30:26 -0400 From: Paul Cercueil To: Ralf Baechle , Michael Turquette , Stephen Boyd , Rob Herring Cc: Paul Burton , Maarten ter Huurne , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux-clk@vger.kernel.org, Paul Cercueil Subject: [PATCH v3 02/18] clk: ingenic: Fix recalc_rate for clocks with fixed divider Date: Sun, 2 Jul 2017 18:30:00 +0200 Message-Id: <20170702163016.6714-3-paul@crapouillou.net> In-Reply-To: <20170702163016.6714-1-paul@crapouillou.net> References: <20170607200439.24450-2-paul@crapouillou.net> <20170702163016.6714-1-paul@crapouillou.net> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 868 Lines: 30 Previously, the clocks with a fixed divider would report their rate as being the same as the one of their parent, independently of the divider in use. This commit fixes this behaviour. This went unnoticed as neither the jz4740 nor the jz4780 CGU code have clocks with fixed dividers yet. Signed-off-by: Paul Cercueil --- drivers/clk/ingenic/cgu.c | 2 ++ 1 file changed, 2 insertions(+) v2: No changes v3: No changes diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index e8248f9185f7..eb9002ccf3fc 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -328,6 +328,8 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) div *= clk_info->div.div; rate /= div; + } else if (clk_info->type & CGU_CLK_FIXDIV) { + rate /= clk_info->fixdiv.div; } return rate; -- 2.11.0