Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752466AbdGCDVW (ORCPT ); Sun, 2 Jul 2017 23:21:22 -0400 Received: from mail-ve1eur01on0050.outbound.protection.outlook.com ([104.47.1.50]:15744 "EHLO EUR01-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752413AbdGCDVT (ORCPT ); Sun, 2 Jul 2017 23:21:19 -0400 From: "A.s. Dong" To: Stephen Boyd , Dong Aisheng CC: "linux-clk@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "mturquette@baylibre.com" , "shawnguo@kernel.org" , "Anson Huang" , Jacky Bai Subject: RE: [PATCH 4/9] clk: imx: add pllv4 support Thread-Topic: [PATCH 4/9] clk: imx: add pllv4 support Thread-Index: AQHSzYN8RV9x7DCYVEawRMTmSUtZjKItNp6AgAB+aYCAELQpAIADUipg Date: Mon, 3 Jul 2017 03:21:16 +0000 Message-ID: References: <1494856763-6543-1-git-send-email-aisheng.dong@nxp.com> <1494856763-6543-5-git-send-email-aisheng.dong@nxp.com> <20170620015917.GO4493@codeaurora.org> <20170620093143.GD6805@b29396-OptiPlex-7040> <20170701003642.GS22780@codeaurora.org> In-Reply-To: <20170701003642.GS22780@codeaurora.org> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: codeaurora.org; dkim=none (message not signed) header.d=none;codeaurora.org; dmarc=none action=none header.from=nxp.com; x-originating-ip: [199.59.231.64] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AM3PR04MB1315;7:P4DM7gxQcZPJ+tonXuUCcdrDV1pvZMhKMBMg8DfalYiU87G/GDLbsleAsQKI2HsclTGAHaFVaqHbXdq2XxwQj5dH1HlBbWKq1Ln+VI4IGl94TDtfmZV4GTXS/C5lUPvcVl21j+O5NDoTA2gTzthhtO8enCZLqEQJRsGY2fJjw9C/Rq/cKpHqVY3s5CUN03lVxv9n0cn7K+CXm/WE0yCWOsHU1xkDQjHDL+aooiYIxzWQFqT7topVi4q3xN3IoNARhu58tazftKfdDNUwhO4H979lrr6vml/Jh3gDXBtbrNj2dRKcFWEhIiaTyZXfEpE1OJLpq/fgv/SKb7ohU3WJgPj7RIvGcjr/NPhtqXdktrGKxa7msEvgVsu+G2/tcaaWFosMd20Zy3KJymCYelQhXjG/kYwW6rwvoP/V9aqZPwutah9cTdZUiHF0YR/2qLwofgYtz4nuXx7TGxVgLf/cglEF40+LSZ8xCzE22g5D44zFF/hXhFnfRp0LqTYEH12O+ZNm8QnLmnuNo0t2Lm9AdF6ndNSDp2MvNc2fbXPvDEe3o/55k7idxJvU9B60FdbFfpzddIKiq/RjmEC8MeG/3/H8hx5JLrCRL1SnhRHF8nkGqz1HEtRbAKSuX67aYYgphb4OJB0+NAPkNXSfhsS7x3mAxOEAXNv5F/+mcKo/fFPozmYCDCIfsX5XMu20OZUW0vrnnOrtRaV75qTyHgYQQMt+NIHXRG6gQSVtFwnGti80ajnyl9xS2IjngrgrPU2LCu2rAOyvKcSkR8jSksqiFy32+YgErgbXFmCQeRTOCss= x-forefront-antispam-report: SFV:SKI;SCL:-1SFV:NSPM;SFS:(10009020)(6009001)(39850400002)(39840400002)(39400400002)(39450400003)(39410400002)(39860400002)(13464003)(377454003)(24454002)(54906002)(229853002)(38730400002)(6436002)(99286003)(9686003)(7696004)(106356001)(55016002)(2900100001)(74316002)(5660300001)(6506006)(66066001)(6246003)(76176999)(53936002)(53546010)(2950100002)(3846002)(54356999)(102836003)(50986999)(6116002)(39060400002)(3660700001)(86362001)(189998001)(478600001)(8936002)(93886004)(2906002)(3280700002)(4326008)(25786009)(14454004)(5250100002)(33656002)(7736002)(81166006)(305945005)(8676002);DIR:OUT;SFP:1101;SCL:1;SRVR:AM3PR04MB1315;H:AM3PR04MB306.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:ovrnspm;PTR:InfoNoRecords;LANG:en; x-ms-office365-filtering-correlation-id: 6d5d9ea0-d4f5-4c59-644d-08d4c1c290f5 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254075)(48565401081)(300000503095)(300135400095)(2017052603031)(201703131423075)(201703031133081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);SRVR:AM3PR04MB1315; x-ms-traffictypediagnostic: AM3PR04MB1315: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(133145235818549)(236129657087228)(9452136761055)(258649278758335); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(100000703101)(100105400095)(93006095)(93001095)(6055026)(6041248)(20161123562025)(20161123560025)(20161123558100)(20161123555025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123564025)(6072148)(100000704101)(100105200095)(100000705101)(100105500095);SRVR:AM3PR04MB1315;BCL:0;PCL:0;RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);SRVR:AM3PR04MB1315; x-forefront-prvs: 035748864E spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jul 2017 03:21:16.4478 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB1315 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v633LR1U006954 Content-Length: 1584 Lines: 47 > -----Original Message----- > From: Stephen Boyd [mailto:sboyd@codeaurora.org] > Sent: Saturday, July 01, 2017 8:37 AM > To: Dong Aisheng > Cc: A.s. Dong; linux-clk@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com; > shawnguo@kernel.org; Anson Huang; Jacky Bai > Subject: Re: [PATCH 4/9] clk: imx: add pllv4 support > > On 06/20, Dong Aisheng wrote: > > On Mon, Jun 19, 2017 at 06:59:17PM -0700, Stephen Boyd wrote: > > > On 05/15, Dong Aisheng wrote: > > > > + > > > > + if (clk_pllv4_is_enabled(hw)) { > > > > + WARN(1, "clk_pllv4: can't change rate when pll is > enabled"); > > > > + return -EINVAL; > > > > > > Sad, CLK_SET_RATE_GATE isn't working for you I suppose? > > > > > > > CLK_SET_RATE_GATE can't work in early stage before running > clk_disable_unused. > > At that point, the clock tree state is still not consistent with HW. > > e.g. prepare/enable count is still zero but it's actually enabled due > > to reset state or bootloader. > > > > The code here is adding a double check in case user sets rate in early > stage. > > > > However, probably it could also be moved into clock core as it's not > > platform dependant behavior? > > > > Ok. It would be good to fix the core framework to synchronize the > prepared/enabled state at registration time so we don't need this check > in the driver. > I will prepare a core fix later and remove these checks first. Regards Dong Aisheng > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a > Linux Foundation Collaborative Project