Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752323AbdGDXEd (ORCPT ); Tue, 4 Jul 2017 19:04:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34932 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752214AbdGDXEc (ORCPT ); Tue, 4 Jul 2017 19:04:32 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 2766B4E4C6 Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=mpatocka@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 2766B4E4C6 Date: Tue, 4 Jul 2017 19:04:23 -0400 (EDT) From: Mikulas Patocka X-X-Sender: mpatocka@file01.intranet.prod.int.rdu2.redhat.com To: Thomas Gleixner cc: Ingo Molnar , Bernhard Held , Andy Lutomirski , Borislav Petkov , Andrew Morton , Brian Gerst , Linus Torvalds , "H. Peter Anvin" , Peter Zijlstra , "Luis R. Rodriguez" , Denys Vlasenko , Josh Poimboeuf , "linux-kernel@vger.kernel.org" Subject: [PATCH v3] X86: don't report PAT on CPUs that don't support it In-Reply-To: Message-ID: References: <3d69fb9d-651a-8266-8e00-789fedd74659@gmx.de> User-Agent: Alpine 2.02 (LRH 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 04 Jul 2017 23:04:32 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 6460 Lines: 214 On Tue, 4 Jul 2017, Thomas Gleixner wrote: > On Mon, 3 Jul 2017, Mikulas Patocka wrote: > > Is there any progress with this patch? Will you accept it or do you want > > some changes to it? > > Aside of the unparseable changelog, that patch is mostly duct tape. > > 1) __pat_enabled should be renamed to pat_disabled, as that is the actual > purpose of that variable > > 2) Making the call to init_cache_modes() conditional in setup_arch() is > pointless. init_cache_modes() has it's own protection against multiple > invocations. > > 3) It adds yet another invocation of init_cache_modes() instead of getting > rid of the ones in pat_disable() and the pat disabled case in pat_init(). > > I've reworked the whole thing into the patch below. > > Thanks, > > tglx Yes - renaming __pat_enabled to pat_disabled is a good thing. Just one more change - init_cache_modes() is protected against multiple calls, but pat_bsp_init() calls __init_cache_modes() (not init_cacha_modes()). The generic code would call init_cache_modes() later and init_cache_modes() would do the initialization again - it would be mostly harmless because it would just read the pat MSR that pat_bsp_init have written and call __init_cache_modes() with the same value - the symptom is that on machines with PAT we see this line twice in the syslog: [ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WC UC- WT [ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WC UC- WT I fixed this double initialization by moving the variable init_cm_done to file scope and setting it in __init_cache_modes(). Mikulas 8<--------------------- Subject: x86/mm/pat: Don't report PAT on CPUs that don't support it From: Mikulas Patocka Date: Tue, 6 Jun 2017 18:49:39 -0400 (EDT) The pat_enabled() logic is broken on CPUs which do not support PAT and where the initialization code fails to call pat_init(). Due to that the enabled flag stays true and pat_enabled() returns true wrongfully. As a consequence the mappings, e.g. for Xorg, are set up with the wrong caching mode and the required MTRR setups are omitted. To cure this the following changes are required: 1) Make pat_enabled() return true only if PAT initialization was invoked and successful. 2) Invoke init_cache_modes() unconditionally in setup_arch() and remove the extra callsites in pat_disable() and the pat disabled code path in pat_init(). Also rename __pat_enabled to pat_disabled to reflect the real purpose of this variable. Signed-off-by: Mikulas Patocka Cc: Bernhard Held Cc: Toshi Kani Cc: Peter Zijlstra Cc: Brian Gerst Cc: "Luis R. Rodriguez" Cc: Borislav Petkov Cc: Andy Lutomirski Cc: Josh Poimboeuf Cc: Denys Vlasenko Cc: Andrew Morton Cc: Linus Torvalds Cc: stable@vger.kernel.org # v4.2+ --- arch/x86/include/asm/pat.h | 1 + arch/x86/kernel/setup.c | 7 +++++++ arch/x86/mm/pat.c | 28 ++++++++++++---------------- 3 files changed, 20 insertions(+), 16 deletions(-) Index: linux-2.6/arch/x86/include/asm/pat.h =================================================================== --- linux-2.6.orig/arch/x86/include/asm/pat.h +++ linux-2.6/arch/x86/include/asm/pat.h @@ -7,6 +7,7 @@ bool pat_enabled(void); void pat_disable(const char *reason); extern void pat_init(void); +extern void init_cache_modes(void); extern int reserve_memtype(u64 start, u64 end, enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm); Index: linux-2.6/arch/x86/kernel/setup.c =================================================================== --- linux-2.6.orig/arch/x86/kernel/setup.c +++ linux-2.6/arch/x86/kernel/setup.c @@ -1076,6 +1076,13 @@ void __init setup_arch(char **cmdline_p) max_possible_pfn = max_pfn; /* + * This call is required when the CPU does not support PAT. If + * mtrr_bp_init() invoked it already via pat_init() the call has no + * effect. + */ + init_cache_modes(); + + /* * Define random base addresses for memory sections after max_pfn is * defined and before each memory section base is used. */ Index: linux-2.6/arch/x86/mm/pat.c =================================================================== --- linux-2.6.orig/arch/x86/mm/pat.c +++ linux-2.6/arch/x86/mm/pat.c @@ -37,14 +37,14 @@ #undef pr_fmt #define pr_fmt(fmt) "" fmt -static bool boot_cpu_done; - -static int __read_mostly __pat_enabled = IS_ENABLED(CONFIG_X86_PAT); -static void init_cache_modes(void); +static bool __read_mostly boot_cpu_done; +static bool __read_mostly pat_disabled = !IS_ENABLED(CONFIG_X86_PAT); +static bool __read_mostly pat_initialized; +static bool __read_mostly init_cm_done; void pat_disable(const char *reason) { - if (!__pat_enabled) + if (pat_disabled) return; if (boot_cpu_done) { @@ -52,10 +52,8 @@ void pat_disable(const char *reason) return; } - __pat_enabled = 0; + pat_disabled = true; pr_info("x86/PAT: %s\n", reason); - - init_cache_modes(); } static int __init nopat(char *str) @@ -67,7 +65,7 @@ early_param("nopat", nopat); bool pat_enabled(void) { - return !!__pat_enabled; + return pat_initialized; } EXPORT_SYMBOL_GPL(pat_enabled); @@ -205,6 +203,8 @@ static void __init_cache_modes(u64 pat) update_cache_mode_entry(i, cache); } pr_info("x86/PAT: Configuration [0-7]: %s\n", pat_msg); + + init_cm_done = true; } #define PAT(x, y) ((u64)PAT_ ## y << ((x)*8)) @@ -225,6 +225,7 @@ static void pat_bsp_init(u64 pat) } wrmsrl(MSR_IA32_CR_PAT, pat); + pat_initialized = true; __init_cache_modes(pat); } @@ -242,10 +243,9 @@ static void pat_ap_init(u64 pat) wrmsrl(MSR_IA32_CR_PAT, pat); } -static void init_cache_modes(void) +void init_cache_modes(void) { u64 pat = 0; - static int init_cm_done; if (init_cm_done) return; @@ -287,8 +287,6 @@ static void init_cache_modes(void) } __init_cache_modes(pat); - - init_cm_done = 1; } /** @@ -306,10 +304,8 @@ void pat_init(void) u64 pat; struct cpuinfo_x86 *c = &boot_cpu_data; - if (!pat_enabled()) { - init_cache_modes(); + if (pat_disabled) return; - } if ((c->x86_vendor == X86_VENDOR_INTEL) && (((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||