Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753049AbdGFGQu (ORCPT ); Thu, 6 Jul 2017 02:16:50 -0400 Received: from mailgw01.mediatek.com ([218.249.47.110]:53493 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752886AbdGFGQs (ORCPT ); Thu, 6 Jul 2017 02:16:48 -0400 Message-ID: <1499321801.22478.12.camel@mhfsdcap03> Subject: Re: [PATCH v3 2/6] pwm: mediatek: fix pwm source clock selection From: Zhi Mao To: Matthias Brugger CC: , Thierry Reding , Rob Herring , Mark Rutland , , , , , , , , , , Date: Thu, 6 Jul 2017 14:16:41 +0800 In-Reply-To: References: <1498802721-32455-1-git-send-email-zhi.mao@mediatek.com> <1498802721-32455-3-git-send-email-zhi.mao@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1423 Lines: 43 On Wed, 2017-07-05 at 13:09 +0200, Matthias Brugger wrote: > > On 06/30/2017 08:05 AM, Zhi Mao wrote: > > In original code, the pwm output frequency is not correct > > when set bit<3>=1 to PWMCON register. > > > > Signed-off-by: Zhi Mao > > --- > > drivers/pwm/pwm-mediatek.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c > > index 5c11bc7..d08b5b3 100644 > > --- a/drivers/pwm/pwm-mediatek.c > > +++ b/drivers/pwm/pwm-mediatek.c > > @@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, > > if (clkdiv > 7) > > return -EINVAL; > > > > - mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv); > > + mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); > > Just for clarification, BIT(15) enables old PWM mode, which ignores > CLKSEL (BIT(3)). Therefore setting BIT(3) does not have any effect and > can be discarded. > > Am I correct? I took mt7623n datasheet for reference. > > Regards, > Matthias > Yes, remove setting bit<3> will not take any effect. PWMCON bit<3> is pwm source clock selecting register. You can check the datasheet of MT7623 for details. Regards Zhi > > mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution); > > mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution); > > > >