Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751878AbdGFO1J (ORCPT ); Thu, 6 Jul 2017 10:27:09 -0400 Received: from mail-oi0-f67.google.com ([209.85.218.67]:34820 "EHLO mail-oi0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750922AbdGFO1I (ORCPT ); Thu, 6 Jul 2017 10:27:08 -0400 MIME-Version: 1.0 In-Reply-To: References: <20170705071215.17603-1-tfiga@chromium.org> <20170705071215.17603-2-tfiga@chromium.org> <20170705151728.GA2479@lst.de> <20170705172019.GB5246@lst.de> From: Arnd Bergmann Date: Thu, 6 Jul 2017 16:27:06 +0200 X-Google-Sender-Auth: ykD4iKqqjmLDkR-5mP899c4nUm4 Message-ID: Subject: Re: [RFC PATCH 1/5] base: dma-mapping: Export commonly used symbols To: Tomasz Figa Cc: Sakari Ailus , Christoph Hellwig , "open list:IOMMU DRIVERS" , "linux-kernel@vger.kernel.org" , Marek Szyprowski , Robin Murphy , Greg Kroah-Hartman , Joerg Roedel , Will Deacon , Vineet Gupta , Hans-Christian Noren Egtvedt , Mitchel Humpherys , Krzysztof Kozlowski , Hans Verkuil , Pawel Osciak , Laurent Pinchart , Linux Media Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2309 Lines: 45 On Thu, Jul 6, 2017 at 4:06 PM, Tomasz Figa wrote: > On Thu, Jul 6, 2017 at 11:02 PM, Arnd Bergmann wrote: >> On Thu, Jul 6, 2017 at 3:49 PM, Tomasz Figa wrote: >>> On Thu, Jul 6, 2017 at 10:31 PM, Tomasz Figa wrote: >> >>>> On the other hand, if it's strictly about base/dma-mapping, we might >>>> not need it indeed. The driver could call iommu-dma helpers directly, >>>> without the need to provide its own DMA ops. One caveat, though, we >>>> are not able to obtain coherent (i.e. uncached) memory with this >>>> approach, which might have some performance effects and complicates >>>> the code, that would now need to flush caches even for some small >>>> internal buffers. >>> >>> I think I should add a bit of explanation here: >>> 1) the device is non-coherent with CPU caches, even on x86, >>> 2) it looks like x86 does not have non-coherent DMA ops, (but it >>> might be something that could be fixed) >> >> I don't understand what this means here. The PCI on x86 is always >> cache-coherent, so why is the device not? >> >> Do you mean that the device has its own caches that may need >> flushing to make the device cache coherent with the CPU cache, >> rather than flushing the CPU caches? > > Sakari might be able to explain this with more technical details, but > generally the device is not a standard PCI device one might find on > existing x86 systems. > > It is some kind of embedded subsystem that behaves mostly like a PCI > device, with certain exceptions, one being the lack of coherency with > CPU caches, at least for certain parts of the subsystem. The reference > vendor code disables the coherency completely, for reasons not known > to me, but AFAICT this is the preferred operating mode, possibly due > to performance effects (this is a memory-heavy image processing Ok, got it. I think something similar happens on integrated GPUs for a certain CPU family. The DRM code has its own ways of dealing with this kind of device. If you find that the hardware to be closely related (either the implementation, or the location on the internal buses) to the GPU on this machine, I'd recommend having a look in drivers/gpu/drm to see how it's handled there, and if that code could be shared. Arnd