Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752559AbdGGISX (ORCPT ); Fri, 7 Jul 2017 04:18:23 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:36395 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750977AbdGGIST (ORCPT ); Fri, 7 Jul 2017 04:18:19 -0400 Subject: Re: [PATCH 8/8] ARM: dts: stm32: add support of exti on stm32h743 pinctrl To: Ludovic Barre , Thomas Gleixner , Jason Cooper , Marc Zyngier CC: Maxime Coquelin , , References: <1499412391-25480-1-git-send-email-ludovic.Barre@st.com> <1499412391-25480-9-git-send-email-ludovic.Barre@st.com> From: Alexandre Torgue Message-ID: <743facf9-6c85-fa38-280f-86e477f0f6ce@st.com> Date: Fri, 7 Jul 2017 10:16:52 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <1499412391-25480-9-git-send-email-ludovic.Barre@st.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG7NODE3.st.com (10.75.127.21) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-07-07_04:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3211 Lines: 127 Hi Ludovic On 07/07/2017 09:26 AM, Ludovic Barre wrote: > From: Ludovic Barre > > Signed-off-by: Ludovic Barre > --- Can you fill commit message please > arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi > index fcc1e06..8854d26 100644 > --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi > @@ -49,6 +49,8 @@ > #size-cells = <1>; > compatible = "st,stm32h743-pinctrl"; > ranges = <0 0x58020000 0x3000>; > + interrupt-parent = <&exti>; > + st,syscfg = <&syscfg 0x8>; > pins-are-numbered; > > gpioa: gpio@58020000 { > @@ -57,6 +59,8 @@ > reg = <0x0 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOA"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > gpiob: gpio@58020400 { > @@ -65,6 +69,8 @@ > reg = <0x400 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOB"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > gpioc: gpio@58020800 { > @@ -73,6 +79,8 @@ > reg = <0x800 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOC"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > gpiod: gpio@58020c00 { > @@ -81,6 +89,8 @@ > reg = <0xc00 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOD"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > gpioe: gpio@58021000 { > @@ -89,6 +99,8 @@ > reg = <0x1000 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOE"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > gpiof: gpio@58021400 { > @@ -97,6 +109,8 @@ > reg = <0x1400 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOF"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > gpiog: gpio@58021800 { > @@ -105,6 +119,8 @@ > reg = <0x1800 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOG"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > gpioh: gpio@58021c00 { > @@ -113,6 +129,8 @@ > reg = <0x1c00 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOH"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > gpioi: gpio@58022000 { > @@ -121,6 +139,8 @@ > reg = <0x2000 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOI"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > gpioj: gpio@58022400 { > @@ -129,6 +149,8 @@ > reg = <0x2400 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOJ"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > gpiok: gpio@58022800 { > @@ -137,6 +159,8 @@ > reg = <0x2800 0x400>; > clocks = <&timer_clk>; > st,bank-name = "GPIOK"; > + interrupt-controller; > + #interrupt-cells = <2>; > }; > > usart1_pins: usart1@0 { >